Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising opening a block family associated with the memory device; initialize a timer associated with the block family; assigning a plurality of cursors to the block family; responsive to programming a first block associated with a first cursor of the memory device, associating the first block with the block family; responsive to programming a second block associated with a second cursor of the memory device, associating the second block with the block family; and responsive to detecting expiration of the timer, closing the block family.

Abstract: A storage device includes; an interface receiving data and a corresponding LBA from a host, wherein the data includes at least one of first data having a stream ID and second data lacking a stream ID, a nonvolatile memory (NVM) device including at least one nonvolatile memory configured to store the data, and a LBA predictor configured to provide a predicted stream ID for the second data using a neural network model operating in response to at least one feature associated with LBA values received by the storage device from the host, wherein the first data is stored in the NVM device using the stream ID, and the data is stored in the NVM device using the predicted stream ID.

Abstract: Protecting data stored on a storage system through the use of different storage levels, including: creating a snapshot of a dataset stored on a storage system, wherein the snapshot includes user data and metadata, and wherein the metadata describes the storage layout of the dataset, offloading the snapshot to a first storage level storage system, and migrating, in accordance with a lifecycle policy, the snapshot from the first storage level storage system onto a second storage level storage system.

Abstract: A data storage environment can include one or more virtual machines instantiated on a host computing device. Based on physical location data of the one or more virtual machines received from the host computing device, a storage manager can control the performance of a secondary copy operation on one or more storage units that store virtual machine data associated with the one or more virtual machines and/or the performance of a secondary copy operation on the one or more virtual machines.

Abstract: A system and method determining a Chain Identification Number (CID) of a source snapshot to be replicated from a source site to a target site of a virtual computing system, determining a predetermined number of potential reference snapshots based on the CID of the source snapshot, computing a closeness value between the source snapshot and each of the potential reference snapshots, and creating a list of the potential reference snapshots based on the closeness value of each of the potential reference snapshots. One snapshot from the list is selected as a reference snapshot. The source snapshot is replicated to the target site based on the reference snapshot.

Abstract: A method and apparatus for performing block management regarding a non-volatile memory are provided. The method includes: determining whether a first blank block belongs to a cold block group or a hot block group according to an erase count of the first blank block; in response to the first blank block belonging to the cold block group, selecting the first blank block from a plurality of blank blocks as a target block, for performing data writing; according to at least one characteristic parameter regarding first data to be written, determining whether the first data belongs to a cold data group or a hot data group; and in response to the first data belonging to the hot data group, writing the first data into the first blank block to use the first blank block as a data block of the first data.

Abstract: A system and method for simultaneously programming flash memory devices in a computing device is disclosed. The computing system includes a switching unit that includes an input and multiple outputs. The switching unit connects the input to one or more of the outputs. Each of the flash memory devices is coupled to one of the outputs of the switching unit. A control bus is coupled to the switching unit. The control bus carries a control signal to select one or more of the outputs for connection to the input. A programming interface bus is coupled to the input of the switching unit. A controller is coupled to the control bus and the programming interface bus. The controller selects the memory devices for providing programming over the programming interface bus.

Abstract: A storage system and method for maintaining uniform hot count distribution using smart stream block exchange are provided. In one embodiment, a rate at which a stream is requesting blocks from a plurality of blocks is determined, and a block from the plurality of blocks is selected for the stream based on the rate at which the stream is requesting blocks. Other embodiments are provided.

Abstract: A magazine-based data storage library in connection with a disk drive-based archive storage system is described that essentially generates parity data for tape formatted data streams (stored to tape cartridges) that do not align by way of data blocks or file marks. Data streams intended for tape storage sent to tape cartridges are also sent to a disk drive storage system via an encoder where parity of the data streams can be generated. More specifically, the encoder digitally formats tape blocks and tape marks (as well as other tape formatted structure) in a digital stream of data that can be added to other encoded digital streams of data to generate parity. To reconstruct a specific tape cartridge from a tape set, the encoded data from each of the tapes in the tape set are subtracted from the parity data and the remaining encoded data is decoded and sent to a designated tape cartridge.

Abstract: Systems and methods for scalable shared memory among networked devices comprising IP addressable memory blocks is disclosed. The disclosed systems and methods comprise a communications network, one or more memory lending devices, each comprising one or more allocated and/or available uniformly sized blocks of memory remotely lendable over the communications network, wherein each of the one or more blocks of memory are uniquely addressable over the communications network using an Internet Protocol (IP) destination address. The systems and methods comprise further comprise at least one memory borrowing device comprising one or more remote blocks of memory allocated (loaned) thereto, wherein the at least one memory borrowing device is configured to individually access each of the one or more remote blocks of memory allocated thereto over the communications network using a unique Internet Protocol (IP) destination address.

Abstract: A memory system includes a memory device including multiple memory blocks and a controller that groups the multiple memory blocks into a plurality of super blocks according to a specific condition, each of the super blocks including two or more memory blocks, sorts a mixed super block among the super blocks, the mixed super block including a source block and a general block, the source block being a memory block having a read count equal to or greater than a reference value, the general block being a memory block having a read count smaller than the reference value, collects and regroups two or more source blocks, included in two or more mixed super blocks, into one or more source super blocks according to the specific condition, and moves valid data of the one or more source super blocks to one or more general super blocks each including general blocks only.

Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.

Abstract: A computer system having a host coupled to a storage device via a peripheral component interconnect express bus. The host communicates with the storage device in accordance with a non-volatile memory host controller interface specification. The storage device stores versions of meta data sequentially in a portion of a volatile memory that is protected against power failure using a power hold-up module. In response to a sudden power loss, the power hold-up module provides sufficient energy to support operations to copy the content from the portion of the volatile memory into a non-volatile memory. During a startup process, the content is retrieved from the non-volatile memory; and a binary search is performed to locate, within the content, the latest, valid version of the meta data to continue operations interrupted by the power loss.

Abstract: Various implementations described herein relate to systems and methods for predicting and managing drive hazards for Solid State Drive (SSD) devices in a data center, including receiving telemetry data corresponding to SSDs, determining future hazard of one of those SSDs based on an a-priori model or machine learning, and causing migration of data from that SSD to another SSD.

Abstract: A data processing apparatus is provided. It includes cache circuitry to store a plurality of items, each having an associated indicator. Processing circuitry executes instructions using at least some of the plurality of items. Fill circuitry inserts a new item into the cache circuitry. Eviction circuitry determines which of the plurality of items is to be a victim item based on the indicator, and evicts the victim item from the cache circuitry. Detection circuitry detects a state of the processing circuitry at a time that the new item is inserted into the cache circuitry, and sets the indicator in dependence on the state.

Abstract: A control apparatus includes a storage that stores multiple parameters, a nonvolatile memory that is rewritable, and a control circuit that writes on the nonvolatile memory a target parameter from among the parameters. The parameter includes a parameter address indicating a storage location on the storage and at least one piece of parameter data. A control bit that is 0 or 1 is arranged in a parameter address or parameter data. The control circuit writes the parameter if the control bit is 1.

Abstract: An information processing apparatus which is capable of preventing a malfunction of a storage using flash memory caused by a decrease in the number of free blocks. The information processing apparatus controls a storage that includes a nonvolatile memory and a memory controller that controls the nonvolatile memory. The number of free blocks in the nonvolatile memory is detected, and in accordance with the detected number of free blocks, the memory controller is instructed to switch to one of the following writing modes: a first writing mode in which the memory controller writes data to the nonvolatile memory without performing garbage collection, and a second writing mode in which the memory control unit writes data to the nonvolatile memory and then performs garbage collection.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller configures a first predetermined memory block and a second predetermined memory block as buffers to receive data from a host device and determines to use the first or the second predetermined memory block to receive the data according to write addresses of a write command received from the host device. When the write addresses indicate that the data to be written by the host device is management data of a file system of the host device, the memory controller writes the data to the first predetermined memory block. When the write addresses indicate that the data to be written by the host device is not the management data of the file system of the host device, the memory controller writes the data to the second predetermined memory block.

Abstract: The data cache of a processor is segregated by execution mode, eliminating the danger of certain malware by no longer sharing the resource. Kernel-mode software can adjust the relative size of the two portions of the data cache, to dynamically accommodate the data-cache needs of varying workloads.

Abstract: A dual in-line memory module (DIMM) includes a memory storage device having data rows and redundant rows. The DIMM further includes a post-package repair module configured to remap an address within the DIMM physical address space from a data row to a redundant row. A memory controller is configured to determine an exact number of un-remapped redundant rows.