Abstract: A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.

Abstract: A manufacturing method of an active matrix substrate which can prevent the complexity of manufacturing processes, widens the range of material choice and allows high manufacturing yield, and a manufacturing method of a liquid crystal display using such active matrix substrate. Conductive colored layers (606 to 608) functioning as pixel electrodes and color filters are formed by a process of discharging, by an ink jet method, a mixed ink of coloring material and conductive material to the formation area of a pixel electrode to be connected electrically to an active element (602).

Abstract: A method of performing irradiation of laser light is given as a method of crystallizing a semiconductor film. However, if laser light is irradiated to a semiconductor film, the semiconductor film is instantaneously melted and expands locally. The temperature gradient between a substrate and the semiconductor film is precipitous, distortions may develop in the semiconductor film. Thus, the film quality of the crystalline semiconductor film obtained will drop in some cases. With the present invention, distortions of the semiconductor film are reduced by heating the semiconductor film using a heat treatment process after performing crystallization of the semiconductor film using laser light. Compared to the localized heating due to the irradiation of laser light, the heat treatment process is performed over the entire substrate and semiconductor film. Therefore, it is possible to reduce distortions formed in the semiconductor film and to increase the physical properties of the semiconductor film.

Abstract: A chip-type LED including a LED element and a tubular vessel accommodating the LED element therein, wherein the vessel has an upper opening and a lower opening, the LED element is positioned between the upper opening and the lower opening such that the LED element emits light toward the upper opening, and the vessel is filled with a light-transmissive resin from the upper opening to the lower opening.

Abstract: Disclosed herein is a method of forming a nonvolatile memory device. The method comprises steps of forming a tunnel insulation pattern and a first floating gate pattern that are sequentially stacked on a semiconductor substrate, and then forming a trench comprising sidewalls aligned with the first floating gate pattern in the semiconductor substrate. Next, a device isolation layer is formed to fill in the trench, and an etch stop layer and a mold layer are sequentially formed on the device isolation layer and on the first floating gate pattern. The mold layer and the etch stop layer are successively patterned to form a groove exposing at least the first floating gate pattern, and a second floating gate pattern is formed to fill in the groove. This method can prevent bridges of floating gate layer that usually occur from regions not being fully etched due to high device integration.

Abstract: A method for manufacturing a gate spacer for self-aligned contacts is provided. A gate stack is formed on a semiconductor substrate. A conformal dielectric layer is then formed over the gate stack. An etch-stop material layer, e.g., a photoresist layer, is formed over the conformal dielectric layer. Next, an upper portion of the etch stop material layer is removed to expose an upper portion of the conformal dielectric layer by techniques such as etching back. Subsequently, the exposed conformal dielectric layer is etched back using the remaining etch-stop material layer as an etch stopper. The remaining etch-stop material layer is removed and the etched-back conformal dielectric layer is again etched back to form a gate spacer.

Abstract: A method for manufacturing a dynamic quantity detection device that is formed by bonding a semiconductor chip that includes a detection element for detecting a dynamic quantity to a stand using a bonding layer includes: forming a semiconductor chip that includes a detection element used for correlating a dynamic quantity to be detected to an electric quantity and a plurality of processing circuit elements used for making up a circuit that processes the electric quantity; placing a bonding layer on a stand; placing the semiconductor chip on the bonding layer; bonding the semiconductor chip to the stand by sintering the bonding layer; and annealing the semiconductor chip in an atmosphere that contains hydrogen in order to cure a change, which is caused during the bonding of the semiconductor chip, in a characteristic of one of the processing circuit elements.

Abstract: An a-Si film (12) formed on an insulating substrate (10) is irradiated with a laser so that the a-Si film (12) is fused and recrystallized to form a p-Si film (13). Projections (100) generated on the p-Si film (13) at this stage are eliminated by irradiation of ion beams at the incident angle of 60° to 90° using an ion milling method to planarize the surface of the p-Si film (13), thereby creating sufficient insulation between the p-Si film (13) and gate electrodes (15).

Abstract: The invention relates to an economical and precise method for the production and configuration of an organic field-effect transistor (OFET) whereby the solubility of at least one functional polymer of an OFET is utilized to such a degree, that the functional polymer is deposited on the OFET, or a substrate, by means of a conventional printing process as for a color.

Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.

Abstract: Embodiments of the present invention include a method of depositing an improved seasoning film. In one embodiment the method includes, prior to performing a substrate processing operation, forming a layer of silicon over an interior surface of the substrate processing chamber as opposed to a layer of silicon oxide. In certain embodiments, the layer of silicon comprises at least 70% atomic silicon, is deposited from a high density silane (SinH2n+2) process gas and/or is deposited from a plasma having a density of at least 1×1011 ions/cm3.

Abstract: A semiconductor device comprising: a base substrate including a semiconductor substrate 10 and a semiconductor element formed on the semiconductor substrate 10; an insulation film 22, 24, 26 formed on the base substrate having an opening 30, 32; and a metal interconnection 42 formed buried in the opening 30, 32 including: a barrier layer 34 formed on an inside wall and a bottom of the opening 30, 32; an adhesion layer 36 containing zirconium formed on the barrier layer 34; and a metal interconnection material 38, 40 containing copper as a main component formed on the barrier layer 36. Whereby the peeling of the copper interconnection in the fabrication process can be prevented. The electro migration resistance and stress migration resistance of the copper interconnection can be further improved.

Abstract: A method for producing a laminate having resin layers and thin metal layers by repeating a process unit comprising a step of laminating a resin layer by applying a resin material, a step of depositing a patterning material on the resin layer and a step of laminating a thin metal layer, predetermined times on a turning support (511), wherein the patterning material is stuck on the surface of the resin layer in a noncontact way. A laminate comprising a large number of laminate units each comprising a resin layer and a thin metal layer divided at an electric insulation stripe part can be produced stably. The laminate is applicable to production of a high performance small capacitor at low cost.

Abstract: A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.

Abstract: Methods are apparatuses are disclosed for an electrical apparatus. The electrical apparatus includes one or more integrated circuits designed at least partly with library cells. Various embodiments cover one or more of virtual buses; virtual tap cells; placement primarily for electrical coupling to a well or substrate; placement at a granularity level of electrical coupling to a well or substrate; metal substantially octagonal via structures; free placement according to a minimum drawing resolution of significant features, cell boundary vertices, and routing wires; and cells permitting overlap.

Abstract: Methods and apparatuses for forming an oxide film. The method includes depositing an oxide film on a substrate using a process gas mixture that comprises a silicon source gas, an oxygen gas, and a hydrogen gas, and a process temperature between 800° C. and 1300° C. During the deposition of the oxide film, the process gas mixture comprises less than 6% oxygen, silicon gas, and predominantly hydrogen.

Abstract: This invention is to support a plate member such as a bonded substrate stack in a horizontal state without coming into contact with one surface of the member and also to efficiently progress separation. Separation is executed while arranging a bonded substrate stack (50) generated by bonding a seed substrate (10) to a handle substrate (20) such that the seed substrate (10) remains on the lower side. At the first stage, the peripheral portion is separated while causing a first substrate support section (101) to chuck and support the central portion of the lower surface of the bonded substrate stack (50). Then, at the second stage, the central portion is separated while causing a second substrate support section (102) to support the lower peripheral portion and side of the bonded substrate stack (50).

Abstract: A stress-relieving heatsink structure and method of forming thereof for an electronic package, for instance, that including a semiconductor chip package which is mounted on a wired carrier, such as a circuitized substrate. The heatsink structure is constituted from a plurality of base structures which are joined along slits so as to impart a degree of flexibility to the electronic package inhibiting the forming of stresses tending to cause delamination of the package components.

Abstract: It is an object of the present invention to adjust the transfer environment of a substrate in order to prevent contamination of the substrate surface by impurities. A semiconductor manufacturing apparatus comprises a load-lock chamber 1 in which substrate exchange with the outside is performed, a wafer process chamber 2 in which the wafer is subjected to a predetermined processing, and a transfer chamber 3 in which the wafer is transferred between the load-lock chamber 1 and the wafer process chamber 2. In a semiconductor manufacturing method in which this semiconductor manufacturing apparatus is used to treat a substrate, an inert gas (N2) is supplied to and exhausted from the load-lock chamber 1, the transfer chamber 3, and the wafer process chamber 2 while the substrate is being transferred from the load-lock chamber 1 to the wafer process chamber 2 through the transfer chamber 3, and the substrate transfer is carried out with a predetermined pressure maintained.

Abstract: This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.