Patents Examined by Granvill D. Lee, Jr.
-
Patent number: 6818469Abstract: A thin film capacitor is provided with a substrate having a thickness equal to or more than 2 &mgr;m and equal to or less than 100 &mgr;m; a lower electrode on the substrate, which includes at least a highly elastic electrode and an anti-oxidation electrode on the highly elastic electrode; a dielectric thin film on the first lower electrode; and an upper electrode on the dielectric thin film; wherein the highly elastic electrode is made of a material having a Young's modulus higher than that of the anti-oxidation electrode.Type: GrantFiled: May 27, 2003Date of Patent: November 16, 2004Assignee: NEC CorporationInventors: Toru Mori, Akinobu Shibuya, Shintaro Yamamichi
-
Patent number: 6818479Abstract: A highly moisture-sensitive element and method of making such element includes an encapsulation enclosure encapsulating all of the highly moisture-sensitive electronic devices on a substrate and a sealing material positioned between the substrate and the encapsulation enclosure to form a complete seal between the substrate and the encapsulation enclosure around each highly moisture-sensitive electronic device or around groups of highly moisture-sensitive electronic devices.Type: GrantFiled: April 9, 2003Date of Patent: November 16, 2004Assignee: Eastman Kodak CompanyInventors: Michael L. Boroson, John Schmittendorf, Jeffrey P. Serbicki
-
Patent number: 6815230Abstract: A method and a device are disclosed for transmitting a control signal to an option pad of an integrated circuit chip at its package level. The method includes the steps of: electrically isolating one of a plurality of commonly connected power transmitting pins of the integrated circuit package; connecting the electrically isolated power transmitting pin to the option pad to thereby transmit a control signal from outside through the electrically isolated power transmitting pin to the option pad.Type: GrantFiled: December 28, 2001Date of Patent: November 9, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Dae Park, Uk-Rae Cho
-
Patent number: 6815269Abstract: A thin-film transistor is formed by a polycrystalline silicon film having a thin-film part and a thick-film part, the thin-film part minimally being used as a channel part. The polycrystalline silicon film is formed by laser annealing with an energy density that completely melts the thin-film part but does not completely melt the thick-film part. Because large coarse crystal grains growing from the boundary between the thin-film part and the thick-film part form the channel part, it is possible to use a conventional laser annealing apparatus to easily achieve high carrier mobility and low leakage current and the like.Type: GrantFiled: May 6, 2003Date of Patent: November 9, 2004Assignee: NEC LCD Technologies, Ltd.Inventor: Hiroshi Okumura
-
Patent number: 6815248Abstract: A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.Type: GrantFiled: April 18, 2002Date of Patent: November 9, 2004Assignee: Infineon Technologies AGInventors: Rainer Leuschner, George Stojakovic, Xian J. Ning
-
Patent number: 6812060Abstract: The present invention provides bumpless ultrasonic bonding of flexible wiring board pieces. A metal coating 26 is formed on the surface of a contact region 181 of a metal wiring 28 of each of two flexible wiring board pieces 10, 30 and ultrasonic wave is individually applied by an ultrasonic resonator 45 to the contact regions 181 in contact with each other. The metal coatings 26 are bonded to form a multilayer flexible wiring board 50. The bumpless process eliminates any plating step for forming bumps without being influenced by non-uniformity bump height. A thermoplastic resin film 33 may be formed on the surface of one flexible wiring board piece 30 to bond flexible wiring board pieces 10, 30 by the adhesion of the resin film 33.Type: GrantFiled: October 16, 2000Date of Patent: November 2, 2004Assignee: Sony Chemicals CorporationInventors: Hideyuki Kurita, Hiroyuki Hishinuma
-
Patent number: 6809042Abstract: The present invention provides an oxide superconductor thick film which is formed on a substrate or a board and has a high Jc and Ic and a method for manufacturing the same. Predetermined amounts of materials containing elements of Bi, Pb, Sr, Ca and Cu are weighed, mixed and subjected to steps of calcining, milling, and drying, and thereafter an organic binder and an organic vehicle are added thereto to prepare a (Bi, Pb)2+aSr2Ca2Cu3Oz, superconductive paste, which is applied to the surface of a substrate or a board in a thickness of 260 &mgr;m or more and dried. Thereafter, the paste is first subjected to burning at temperatures of 835° C. to 840° C. for 100 hours, then pressurization, and further burning at temperatures of 835° C. to 840° C. for 100 hours, thereby preparing an oxide superconductor thick film having a film thickness of 130 &mgr;m or more having a high Jc and Ic.Type: GrantFiled: August 26, 2002Date of Patent: October 26, 2004Assignees: Dowa Mining Co., Ltd., Central Research Institute of Electric Power IndustryInventors: Masahiro Kojima, Masakazu Kawahara, Michiharu Ichikawa, Hiroyuki Kado, Masatoyo Shibuya
-
Patent number: 6808992Abstract: A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.Type: GrantFiled: May 15, 2002Date of Patent: October 26, 2004Assignee: Spansion LLCInventors: Kelwin Ko, Shenqing Fang, Angela T. Hui, Hiroyuki Kinoshita, Wenmei Li, Yu Sun, Hiroyuki Ogawa
-
Patent number: 6803309Abstract: A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.Type: GrantFiled: July 3, 2002Date of Patent: October 12, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shih-Wei Chou, Chii-Ming Wu
-
Patent number: 6800541Abstract: A method of irradiation of plural pulse laser beams onto one position of a non-single crystal semiconductor, wherein the pulse laser beams are not higher in energy density than an energy density threshold value necessary for causing a micro-crystallization of the non-single crystal semiconductor.Type: GrantFiled: October 4, 2002Date of Patent: October 5, 2004Assignee: NEC CorporationInventor: Hiroshi Okumura
-
Patent number: 6794291Abstract: An apparatus for processing a semiconductor wafer or similar article includes a reactor having a processing chamber formed by upper and lower rotors. The wafer is supported between the rotors. The rotors are rotated by a spin motor. A processing fluid is introduced onto the top or bottom surface of the wafer, or onto both surfaces, at a central location. The fluid flows outwardly uniformly and in all directions. A wafer support automatically lifts the wafer, so that it can be removed from the reactor by a robot, when the rotors separate from each other after processing.Type: GrantFiled: July 23, 2002Date of Patent: September 21, 2004Assignee: Semitool, Inc.Inventors: Steven L. Peace, Gary L. Curtis, Raymon F. Thompson, Brian Aegerter, Curt T. Dundas
-
Patent number: 6790758Abstract: A process for fabricating a flip-chip substrate with metal bumps thereon. A flip-chip substrate is provided with conductive points thereon and a conductive film is formed over the surface of the flip-chip substrate to cover the conductive points. A photoresist layer is formed over the conductive layer and then patterned to form openings exposing the underlying conductive points. A copper plating is performed to fill the openings as copper bumps. The photoresist layer and the conductive film are removed. Finally, a solder mask layer is formed over the flip-chip substrate and exposing the copper bumps and an anti-oxidation treatment is performed to finish exposing the copper bumps.Type: GrantFiled: November 25, 2002Date of Patent: September 14, 2004Assignee: Silicon Integrated Systems Corp.Inventors: Han-Kun Hsieh, Wei-Feng Lin
-
Patent number: 6784121Abstract: A xerogel aging system includes an aging chamber (190) with inlets and outlet and flows a gel catalyst in gas phase over a xerogel precursor film on a semiconductor wafer. Preferred embodiments use an ammonia and water vapor gas mixture catalyst.Type: GrantFiled: October 23, 1998Date of Patent: August 31, 2004Assignee: Texas Instruments IncorporatedInventors: Changming Jin, Richard Scott List, Joseph D. Luttmer
-
Patent number: 6780694Abstract: A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate.Type: GrantFiled: January 8, 2003Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Omer H. Dokumaci, Jack A. Mandelman, Carl J. Radens
-
Patent number: 6773943Abstract: A display unit having a sufficient luminance and a method of fabricating the display unit are provided. The display unit includes micro-sized semiconductor light emitting devices fixedly arrayed on a plane of a base body of the display unit at intervals. Micro-sized GaN based semiconductor light emitting devices formed by selective growth are each buried in a first insulating layer made from an epoxy resin except an upper end portion and a lower end surface thereof, and electrodes of each of the light emitting devices are extracted. These light emitting devices are fixedly arrayed on the upper plane of the base body at intervals. A second insulating layer made from an epoxy resin is formed on the plane of the base body so as to cover the semiconductor light emitting devices each of which has been buried in the first insulating layer.Type: GrantFiled: March 12, 2003Date of Patent: August 10, 2004Assignee: Sony CorporationInventors: Toyoharu Oohata, Hideharu Nakajima, Yoshiyuki Yanagisawa, Toshiaki Iwafuchi
-
Patent number: 6774056Abstract: A process system for processing a semiconductor wafer or other similar flat workpiece has a head including a workpiece holder. A motor in the head spins the workpiece. A head lifter lowers the head to move the workpiece into a bath of liquid in a bowl. Sonic energy is introduced into the liquid and travels through the liquid to the workpiece, to assist in processing. The head is lifted to bring the workpiece to a rinse position. The bath liquid is drained. The workpiece is rinsed via radial spray nozzles in the base. The head is lifted to a dry position. A reciprocating swing arm sprays a drying fluid onto the bottom surface of the spinning wafer, to dry the wafer.Type: GrantFiled: July 19, 2002Date of Patent: August 10, 2004Assignee: Semitool, Inc.Inventors: Jon Kuntz, Steven Peace, Ed Derks, Brian Aegerter
-
Patent number: 6762116Abstract: A system and method is described for fabricating microcomponents onto pre-existing integrated electronics. One embodiment of the present invention provides additional process steps after completion of all electronics fabrication that may etch trough the oxide of any passivation layer that may be there to the single crystal silicon (SCS) of a silicon on insulator (SOI) integrated circuit. Once at the SCS level of the existing wafer, any number of microcomponents, such as connectors, receptacles, handles, tethers, and the like may preferably be fabricated onto the chip using relatively low temperature and inexpensive processing; thus, preferably preserving the integrity of the preexisting electronics.Type: GrantFiled: June 12, 2002Date of Patent: July 13, 2004Assignee: Zyvex CorporationInventor: George D. Skidmore
-
Patent number: 6753198Abstract: A manufacturing method of an active matrix substrate which can prevent the complexity of manufacturing processes, widens the range of material choice and allows high manufacturing yield, and a manufacturing method of a liquid crystal display using such active matrix substrate. Conductive colored layers (606 to 608) functioning as pixel electrodes and color filters are formed by a process of discharging, by an ink jet method, a mixed ink of coloring material and conductive material to the formation area of a pixel electrode to be connected electrically to an active element (602).Type: GrantFiled: October 16, 2001Date of Patent: June 22, 2004Assignee: Seiko Epson CorporationInventors: Hiroshi Kiguchi, Satoru Katagami, Tomomi Kawase, Hisashi Aruga, Masaharu Shimizu
-
Patent number: 6746884Abstract: In a method of manufacturing matrix electron emitter arrays, each array comprising a plurality of scanning lines formed on a glass substrate and arranged in parallel with each other, a plurality of signal lines formed in a direction to cross the scanning lines and arranged in parallel with each other, and field-emission type electron emitters formed in the pixel areas which are arranged at the intersections of the scanning lines and the signal lines, a pulse voltage with a specific polarity and another pulse voltage with the reverse polarity are applied to any two of the scanning lines and current is caused to flow through electron emitters connected in series-via a signal line, thereby subjecting the conductive thin film constituting an electron emitter to a conductive activation process for forming an electron emitting section.Type: GrantFiled: March 8, 2002Date of Patent: June 8, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Koji Suzuki
-
Patent number: 6737328Abstract: In one aspect, the invention includes a method of forming a, silicon dioxide layer, including: a) forming a high density plasma proximate a substrate, the plasma including silicon dioxide precursors; b) forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and c) while depositing, etching the deposited silicon dioxide with the plasma at an, etch rate; a ratio of the deposition rate to the etch rate being at least: about 4:1. In another aspect, the invention includes a method of forming a silicon dioxide layer, including: a) forming a high density plasma proximate a substrate; b) flowing gases into the plasma, at least some of the gases forming silicon dioxide; c) depositing the silicon dioxide formed from the gases over the substrate; and d) while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C.Type: GrantFiled: February 2, 2000Date of Patent: May 18, 2004Assignee: Micron Technology, Inc.Inventors: Sujit Sharan, Gurtej S. Sandhu