Abstract: A control unit (102) efficiently decodes burst signal transmissions in a TDMA-based telecommunication system (100) by decimating down the number of samples requiring processing during symbol detection. The control unit (102) includes a sampling receiver (304) that inputs burst signals from cable access units, converts them to a pair of baseband quadrature signals, I and Q. The sampling receiver (304) also includes an A/D converter (314) that samples the I and Q signals at preferably four times the symbol rate. A digital signal processor circuit (306) produces a timing error signal for substantially all of the samples. The digital processor circuit (306) also accumulates a timing error sum for each of the four samples. The processor circuit (306) selects the optimum sample as the sample between the samples having the largest positive and negative error sums. The processor circuit (306) also includes a .pi./4-DQPSK differential detector that processes the optimum sample of each symbol for symbol detection.

Abstract: A PN code synchronizing method in spread spectrum communication systems of the present invention calculates a matrix H based on tap locations of a PN code generating shift register, also calculates an internal status of the PN code generating shift register at a time t+M by multiplying an internal status of the PN code generating shift register at a time t by M-th power of the matrix H, and transmits the internal status of the PN code generating shift register at a time t+M to reception side through a synchronous channel. in reception side, a PN code generating shift register therein is set based on the internal status of the PN code generating shift register at a time t+M.

Abstract: A circuit and method of adjusting a sample point for a data stream to account for intersymbol interference is disclosed herein. The system averages the amount of intersymbol interference occurring for a specific data pattern and uses this average value which reflects a phase difference between the leading edges of two pulses to determine at which clock count a sync pulse should issue to sample and read a data value.

Abstract: A signal coding system capable of high efficiency, high quality signal coding is provided. Digital signals represented in the time domain are divided into set time interval data units and output. One output is converted to a digital signal represented in the frequency domain, and the other is output as-is. The energy dispersion of the digital signal represented in the frequency domain is compared with that of the digital signal represented in the time domain, and the digital signal having the least energy dispersion is coded. This coded digital signal is then multiplexed with an identification signal to identify it as a frequency domain or time domain signal, and the resulting multiplexed signal is output.

Abstract: A locally coherent Quadrature Phase Shift Keying (QPSK) detector that uses a normalized fourth power weighting technique to generate an ambiguous local phase reference of a current symbol. A phase adjusted previous symbol reference is used to resolve the ambiguity using differentially coded data and yield current soft symbol information.

Abstract: A carrier recovery circuit includes a correction circuit for correcting phase differences which appear betwen a complex input signal and a local carrier supplied by a local oscillator. The correction circuit defines zones in a plane defined by in-phase components and quadrature components of the complex signal. Each zone includes a respective state of a constellation that is used for encoding the signal during transmission. When a point representing the signal in the I/Q plane is subjected to a decision, the correction circuit produces a correction signal proportional to a measured phase difference. When the point lies outside the zones, the correction circuit produces a correction signal that varies as a function of the measured phase difference to which a weighting factor, dependent on the distance from the point to the nearest zone, is applied. In a first mode the correction circuit corrects either the local oscillator phase or frequency; or in a second mode, corrects the signal phase.

Abstract: A synchronization control method for a synchronous digital hierarchy system includes the steps of: at a first selecting unit, selecting a given number of timing sources, from among a plurality of first timing sources within a main shelf, in accordance with user setting data, and outputting the given number of the selected timing sources; at a first quality data generating unit, outputting quality data of one or more of the selected timing sources when the one or more of the selected timing sources have no quality data; at a second selecting unit, selecting one or more timing sources from among a plurality of second timing sources within a slave shelf when any timing sources set by the user setting data are included in the second timing sources within the slave shelf, and transmitting the selected one or more timing sources to the main shelf; at a second quality data generating unit, outputting the quality data of the one or more timing sources supplied from the second selecting unit, and transmitting the qual

Abstract: In an automobile on-board and/or portable telephone system capable of increasing the capacity of subscribers easily on the basis of changing of information transmission bit rate, spread codes obtained by multiplying orthogonal spread codes (m in number) by a pseudo-random noise series are assigned to individual channels in the same cell in such a manner that the orthogonal spread codes are multiplied by some types of pseudo-random noise series having different phases, thereby making it possible to maintain the number of channels in the same cell at a value which is a multiple of the number of the orthogonal spread codes.

Abstract: A frame synchronization circuit which detects a frame synchronization bit allotted in a particular position within a receiving data string includes a shift register, a synchronization pattern detection circuit and a control circuit. The shift register receives and stores the receiving data string and outputs a parallel data string. The synchronization pattern detection circuit receives the parallel data string outputted from the shift register in synchronization with a clock signal and makes decisions simultaneously on the matching/non-matching of a parallel data string of totally r bits disposed in an n bit cycle within the receiving data string with r kinds of predetermined synchronization patterns of r bits. The control circuit receives an output of the synchronization pattern detection circuit, and outputs either a signal indicative of the in-synchronization state through a terminal or a signal indicative of the out-of-synchronization state through a terminal.

Abstract: A mixed combination strategy combiner for receivers operating in high capacity digital radio links and protected with space or angle diversity is described. The combiner comprises a system which calculates the amplitude dispersion in the spectrum of frequencies of the combined signal and a device which measures the power thereof. On the basis of this information and an appropriate calculation strategy tending to minimize the BER of the equipment, a microprocessor generates signals for gain control of the stage RF of the receivers and for phase shift control for a phase shifter for the local oscillator signal sent to one of the receivers. The calculation strategy consists of minimizing a polynomial function of the power and dispersion values. Dependence of the BER on the f.sub.notch characterizing the dispersion is eliminated, normalizing dispersion in relation to f.sub.notch.

Abstract: A communication system used in a semiconductor device manufacturing equipment includes a master side transmission unit having a master transmitting logic module for transmitting information in an inverted two-successive transmission mode in which information having non-inverted information and inverted information of the non-inverted information as one pair is transmitted and a master receiving logic module, and a plurality of slave side transmission units respectively mounted on a plurality of process units of a cleaning apparatus of the semiconductor device manufacturing equipment and each having a slave transmitting logic module and a slave receiving logic module which receives the non-inverted information and inverted information, for fetching the information when the contents of the non-inverted information and inverted information coincide with each other.

Abstract: An apparatus and method of transmitting digital data over a coaxial cable a noisy environment using several carriers with narrower bandwidths in place of the single carrier with a wide bandwidth. In a frequency spectrum, these several carriers are located between interfering harmonic and spurious noise frequencies generated by the other signals, an particularly clock signals. These narrow signals are then combined for transmission over a cable, substantially reducing noise in the signal recovered at the receiving end.

Abstract: An encoder apparatus is disclosed for encoding a wideband digital information signal. The apparatus comprises an input signal (1) for receiving the wideband digital information signal, a signal splitting unit (2) for splitting the wideband digital information signal into M narrow band sub signals (SB.sub.1 to SB.sub.M). The narrow bands all have a specific constant bandwidth. Further, a scale factor determining unit (6) for determining a scale factor for subsequent signal blocks in each of the sub signals, and a quantization unit (13) for quantizing the samples in a signal block into quantized samples are present. A bit allocation information deriving unit (34,41,48) is present for deriving bit allocation information, the bit allocation information being representative of the number of bits with which samples in a signal block of a sub signal will be represented after quantization in the quantization unit (13).

Abstract: A digital timing recovery circuit for recovering a sampling clock of a playback signal in digital equipment, provides a fast phase obtaining time, reduces a phase error so as to generate a stable sampling clock and a dead zone effect caused by performing a quantization using a limited number of bits in hardware, and includes an analog-to-digital converter, a phase error detector, a phase error comparator, a loop filter, a reference voltage generator, a digital-to-analog converter and a variable voltage oscillator, to thereby reduce the phase obtaining time by varying the bandwidth of the loop filter according to the phase error size detected by the phase error detector and reduce a sampling phase error caused by noise at a constant state.

Abstract: A method and an equipment for monitoring the fill rate of an elastic buffer memory used in a synchronous digital telecommunication system, such as the SDH or SONET system. To enable the monitoring of the fill rate of the channels with less hardware than previously, the fill rate of at least two channels of the same level of hierarchy is monitored on a time-division basis in a monitoring unit common to the channels.

Abstract: A line spectral frequency (LSF) vector quantizer, having particular application in digital cellular networks (DCN), is provided for code excited linear predictive (CELP) speech encoders. The LSF vector quantizer is efficient in terms of bits employed, robust and effective in terms of performance across speakers and handsets, moderate in terms of complexity, and accommodates effective and simple built-in transmission error detection schemes. The LSF vector quantizer employs a minimum number of bits, is of moderate complexity and incorporates built-in error detection capability in order to combat transmission errors. The LSF vector quantizer classifies unquantized line spectral frequencies into four categories, employing different vector quantization tables for each category. Each quantization table is optimized for particular types of vectors. For each category, three split vector codebooks are used with a simplified error measure to find three candidate split quantized vectors.

Abstract: A simultaneous voice and data (SVD) modem includes a preemphasis filter for processing an audio source signal, e.g., a voice signal, before transmission to a far-end SVD-capable modem. The preemphasis filter implements a second order linear predictor in which a quantized set of predictor coefficients are selected directly from the normalized autocorrelation coefficients. In addition, an index is associated with the selected set of predictor coefficients. This index is transmitted to an opposite SVD-capable modem, which thereby allows the opposite SVD-capable modem to select the same set of predictor coefficients for use in recovering the voice signal at the opposite endpoint.

Abstract: In a terminal adapter which is located between a data terminal equipment unit (11) and a data communication network (12) and which includes a buffer memory (22, 27) for memorizing an original data signal sequence sent from each of the data terminal equipment unit and the data communication network, the original data signal sequence is subjected to data compression by a data compression circuit to be thereafter memorized into the buffer memory and to be read out of the buffer memory as a readout data signal sequence. The readout data signal sequence is expanded by a data expansion circuit (32, 35) to be sent to the data terminal equipment unit or the data communication network at a transmission rate matched therewith. The data compression may be executed by the use of an LZ method, a modified LZ method, such as LZW, LZSS, or the like.

Abstract: A novel an improved method of acquisition in a spread spectrum communication system is presented. In the present invention, a large window of PN chip offset hypotheses are searched and if an energy signal is found that might indicate the presence of the pilot signal having one of the chip offsets of the large search window, then a search of a subset of offset hypotheses, or small window, is searched.

Abstract: A PN code acquisition system for Code Division Multiple Access (CDMA) Direct Sequence Spread Spectrum (DSSS) systems, with automatic decision threshold, is based on the combination of the Maximum Likelihood (ML) and Serial Search (SS) acquisition approaches. In contrast to the conventional SS acquisition system, the disclosed system adaptively estimates optimal threshold by exploiting the statistics of the signal and noise, and makes an optimal decision based on the threshold. The system estimates the threshold by employing ML estimation and applies the threshold as in SS acquisition and makes a decision by comparing the updated threshold with the current signal strength. Together with post detection verification logic, this approach will increase detection probability and reduce false alarm probability significantly. An optimum system parameter design approach and the advantages of this approach as compared to conventional approaches (ML or SS acquisition) are demonstrated.