Abstract: A circuit for error correcting a received complex data signal comprises a synchronous detector for recovering an in-phase data component from the received signal and a Hilbert transform filter for estimating the related quadrature component from the recovered in-phase data component, the recovered in-phase data component including a periodically recurring reference signal. A decision feedback loop is periodically operable in response to the reference signal for initially error correcting a selected characteristic of the received signal at a first relatively rapid rate and for subsequently error correcting the selected characteristic at a rate which is less than the first rate and which is dependent upon the estimated S/N ratio of the received signal. In one embodiment, phase errors are corrected at a rate which is also directly related to the value of the estimated quadrature component. In another embodiment, amplitude errors, e.g.

Abstract: A circuit for error correcting a received complex data signal comprises a synchronous detector for recovering an in-phase data component from the received signal and a Hilbert transform filter for estimating the related quadrature component from the recovered in-phase data component, the recovered in-phase data component including a periodically recurring reference signal. A decision feedback loop is periodically operable in response to the reference signal for initially error correcting a selected characteristic of the received signal at a first relatively rapid rate and for subsequently error correcting the selected characteristic at a rate which is less than the first rate and which is dependent upon the estimated S/N ratio of the received signal. In one embodiment, phase errors are corrected at a rate which is also directly related to the value of the estimated quadrature component. In another embodiment, amplitude errors, e.g.

Abstract: In a digital radio receiver, an amplitude limiter circuit (20, 21) is included for producing a constant-amplitude IF signal from a received digitally modulated IF signal. An orthogonal detector (22) orthogonally mixes the constant-amplitude signal with a reference carrier and produces a in-phase baseband signal and a quadrature-phase baseband signal. The baseband signals are converted to first and second digital signals (24, 25) and supplied to multipliers (26, 27), respectively. A logarithmic. detector circuit (30) is coupled to the amplitude limiter (20) for generating a signal representative of the amplitude of the received IF signal. The logarithmic scale of the amplitude signal is converted to linear scale by a logarithmic-to-linear converter circuit (32, 33) and supplied to the multipliers (26,27) in which it is multiplied with the digital baseband signals. The outputs of the multipliers are coupled to an equalizer (28) for eliminating bit errors.

Abstract: An analytical digitizer for signal processing includes a sampler and an analog/digital converter. A first calculating device supplies a first component of the signal made up of a sequence of digital values. Each value is calculated by adding 2h+2 value supplied by the converter weighted with respective non-null integer coefficients a.sub.0, . . . , a.sub.h, a.sub.h, . . . , a.sub.0. A second calculating device supplies a second component of the signal, in phase quadrature to the first, and made up of a sequence of digital values y(t). Each of these values is calculated by adding 2h+2 values supplied by the converter weighted with respective non-null integer coefficients b.sub.0, . . . , b.sub.h-1, -b.sub.h-1, . . . , -b.sub.0. The number and the value of the coefficients are determined by a rigorous method according to the center frequency and the bandwidth of the spectrum of the signal to be processed and according to a fixed limit value for the signal/noise ratio.

Abstract: A simplified transition detector identifies phase reversal without relying upon complex correlation relationships or trellis techniques. Two correlation signals are obtained using tones with a phase difference of .pi./2. Zero-crossing information on the two correlation signals is used to detect phase reversal.

Abstract: A method and apparatus are provided for recovering and tracking the carrier in a QAM communication system, even under heavy interference conditions. A subset of fixed points is defined on an ideal constellation pattern for comparison to the data points in a received signal. The subset includes all of the points intersected by n radii (e.g., the four diagonals) of the constellation pattern. Additional points along the perimeter of the constellation pattern can also be provided in the subset. Data points received via a carrier are correlated with the fixed points of the subset in order to generate an error signal indicative of a phase difference between the fixed points of the subset and the received data points correlated therewith.

Abstract: Selectable demodulation means within a given receiver to demodulate signals potentially subjected to many different types of degradations as typically encountered in mobile communications systems, and to select the best result of provide significant performance improvement is disclosed. In accordance with the method, when an RF signal is received it is sampled and the samples are demodulated. Demodulation is performed using both coherent and non-coherent schemes with the preferred scheme selected according to the quality of performance of each demodulator. Coherent demodulation can provide better performance when the signal is subjected to significant path loss but little fading. Non-coherent demodulation can provide better performance when the signal is subjected to less path loss but significant fading. Details of the method are disclosed.

Abstract: A radio communication system operates between two radio terminals, and/or between a radio terminal and a fixed terminal through a network. In the present disclosure, the switching of codec-release mode and codec mode in the network is controlled by using a specific control line which is installed in addition to a speech line. Thus, when a radio terminal communicates with another radio terminal through a network, no codec is used in the network, and so, speech distortion and signal delay are not deteriorated due to signal conversion by using a codec.

Abstract: Linear and decision feedback equalizers which are communication receivers used in computer systems having an ISI receiver system and analysis paradigm to provide the ability of estimating the performance of these receivers under mismatched channel conditions. The mean square error (MSE) performance of linear and decision feedback equalizers in the presence of arbitrary channel mismatch is presented. A generic equalizer which has feed-forward and feedback taps which are optimized for a mean square error (MSE) criterion. The ability to rapidly predict MSE performance also leads to the real-time adaptation of the equalizer complexity to improve MSE performance, optimal truncation of channel impulse response based on an MSE criterion, and assessing the impact of assuming white noise in a colored noise environment. With the system and method there is a determination of the spectral characteristics of the communication channel during training and/or decoding.

Abstract: A serial communication bus for a motor vehicle subject to different ground voltages on the common line and a transmitting module has a compensation circuit to prevent mismatches which distort pulse current waveforms and cause radiated emissions. When line ground voltage is higher than the transmitter voltage an integrator is used to simulate the line ground voltage and apply that to the transmitter ground. The integrator has a small current source and a very large current sink to follow the line ground potential. The transmitter output is disabled between pulses to avoid increasing the line ground voltage. When line ground voltage is lower than the transmitter voltage, the transmitter is enabled between pulses to feed current to the line to increase its potential.

Abstract: The present invention relates to an audio signal coding and decoding device for coding and decoding an audio signal using an adaptive differential coding system. The audio signal coding and decoding device according to the present invention comprises an adaptive differential pulse code modulation coding device for coding an audio signal, an adaptive differential pulse code modulation decoding device for decoding the audio signal coded, an integrator provided in the preceding stage of the coding device and for decreasing the variation between unit samples of the input audio signal of the coding device, and a differentiator provided in the succeeding stage of the decoding device and for processing the audio signal decoded by the decoding device so that the variation decreased by the integrator is restored to the original one. Since the integrator is provided in the preceding stage of the coding device, the variation between the unit samples of the input audio signal of the coding device is decreased.

Abstract: Feedback signals for use in controlling a variable gain amplifier portion of a radio receiver are obtained from existing automatic gain control signals comprising a part of a time domain equalizer section of a receiver such that bandpass filtering and feedback signal detecting circuitry, along with detector circuitry linearization apparatus required in prior art feedback schemes, can be eliminated from the overall scheme. The resulting apparatus provides a constant level to the input of the incorporated analog-to-digital converter and the resultant loop adapts to changing RF/baseband bandwidths.

Abstract: A data phase alignment circuit (34) is provided to align incoming plesiochronous data with a known clock phase. Multiple phases of a clock signal are provided to a data capture circuit (40), which captures the incoming plesiochronous data with at least one of the clock phases. A data transition decoder (44) then determines the time of data transition with respect to the multiple phases of the clock. The captured data is then realigned with a selected phase of the multiple clock phases by a data retimer circuit (50) and provided as the output (64). The resultant data is therefore aligned with a known phase of the clock signal and is no longer plesiochronous with respect to the clock signal. Data shifting due to data jitter, drift and wander may also be correct with a slip buffer (38).

Abstract: A PSK signal demodulating apparatus having a clock extracting circuit. The clock extracting circuit includes a counter that is operable by a clock having a frequency N time the carrier frequency of a phase modulated signal such as a .pi./4 shift DQPSK modulated wave is latched at the leading edge timing of the above signal thereby to obtain phase data. Also, a difference between these phase data is calculated at mod.2.pi. thereby to extract a clock component.

Abstract: Circuitry is described for providing a telephone line interface circuit of a MODEM for a computer with an AC impedance and DC voltage/current characteristics required by a given type telephone network such that the telephone line interface circuit can be matchingly connected with the given type telephone network. The given type telephone network provides an identification code representative of the required AC impedance and DC voltage/current characteristics. The circuitry comprises a plurality of impedance components that, when connected to the telephone line interface circuit, determine the AC impedance and DC voltage/current characteristics of the telephone line interface circuit. A plurality of terminals are coupled to receive a plurality of control signals associated with the identification code.

Abstract: A method and apparatus for performing frequency acquisition. Frequency acquisition is accomplished by utilizing binary-search techniques with a controller (13), variable digital oscillator (16), frequency detector (11) an incrementor (19) and decrementor (21) and control registers (22). The frequency detector (11) generates an output indicating the relative speed of the variable oscillator (16) with reference to a externally provided signal. Depending on the output of the frequency detector (11 ), the arithmetic logic circuitry (19, 21) will increase or decrease the value in a control register (22), resulting in a corresponding increase or decrease in speed of the variable oscillator (16). The magnitude of changes to the control register (22) is gradually reduced as the steps of frequency detection and arithmetic updates are repeated until the variable oscillator (16) has reached the proper frequency.

Abstract: In order to permit and already occupied frequency spectrum to be utilized for the radio transmission of a data stream without interfering with the services already established there, a plurality of the RF carriers modulated with the data stream are either transmitted in the frequency gap between two adjacent frequency FM services at the same location or in the free frequency ranges at both sides of an FM service, while leaving out its rated frequency occupation. Compared to the level of the RF carrier of the adjacent frequency FM service or the FM service in the middle, the level of the plurality of RF carriers is selected to be sufficiently low in the sense of a signal to noise ratio that is sufficient for FM reception of the FM service or services. Moreover, the mentioned level is selected to be sufficiently high in the sense of noise immunity against locally remote FM services which fall into the frequency range or frequency gap intended for the transmission of the plurality of RF carriers.

Abstract: In a clock recovery system for use in a ring-shaped synchronization network which comprises a master transmission device and a plurality of slave transmission devices, a clock pulse sequence is circulated in a predetermined direction from the master transmission device through the plurality of the slave transmission devices in a normal state and a fault indication signal is transmitted in the predetermined direction from one of the slave transmission devices that detects interruption of the clock pulse sequence. Responsive to the fault indication signal, the master transmission device transmits a switch indication signal in a reverse direction to the one slave transmission device so as to switch the direction of the clock pulse sequence in each slave transmission device. Responsive to the switch indication signal, the one slave transmission device transmits a switch completion signal to the master transmission device in the predetermined direction.

Abstract: An open loop desynchronizer (10) includes a demapper (12) that reads asynchronous data from a synchronous channel (14) and writes this data to a first in first out buffer (18). The demapper (12) decodes deviations from a nominal stuff bit rate that indicates whether fewer or more stuff bits than data bits are needed on the synchronous channel (14) and generates a frequency deviation control signal (20) therefrom. The frequency deviation control signal (20) drives a digital filter (22) and a numerically controlled oscillator (24). The digital filter (22) and numerically controlled oscillator (24) generate a transmit clock (26) that tracks the asynchronous payload rate according to unit pulses on the frequency deviation control signal (20). The first in first out buffer (18) transmits the asynchronous data over a transmit data line (28) according to the asynchronous payload rate generated on the transmit clock (26).

Abstract: Data words are transmitted over a radio channel with a novel modulation scheme which transmits data in parallel. An entire data word is modulated by separating a carrier frequency band into a number of discrete `tones`. Tone T.sub.1 is set to a zero phase shift in order to provide timing in synchronization of the signal. The remaining tones are phase shifted according to a predetermined convention, thereby encoding the bits of the data word. The phase shifts for all tones comprises a spectrum which is transmitted to a receiver simultaneously. A receiver monitors tone T.sub.1 for zero phase shifts to provide synchronization of the signal. The remaining tones are analyzed for their phase shift to provide bits which are assembled into a transmitted data word. Since the bits are transmitted in parallel as the data word, as opposed to conventional modulation schemes, the throughput is increased.