Abstract: A digital information receiver having a single oscillator providing a clock signal to the receiver circuitry. The receiver contains, in addition to the oscillator, an input signal processor, a symbol timing loop, a demodulator, a transport decoder, a transport timing loop, one or more applications decoders and a presentation device. The input signal processor digitizes an input signal and resamples the input signal using an interpolator such that the input signal is optimally sampled. The resampling is controlled by a symbol timing loop. In a first embodiment, the transport timing loop controls the frequency of the oscillator using transmitter timing information contained in the received signal. In a second embodiment, the oscillator is a free running oscillator and the transport timing loop controls a numerically controlled counter that, in turn, controls presentation timing of the information carried by the information in the input signal.

Abstract: A block demodulation method and apparatus that provides for synchronizing bursts of incoming data without a special symbol synchronization word, and minimal frame synchronization overhead. An entire burst, comprising ramp up time, a preamble, guard times, data and ramp down time, is captured and stored in the form of baseband samples of the signal burst. The burst samples are then filtered to reduce pattern jitter. Thereafter, the samples are squared to derive the symbol clock. Then, the samples are differenced and cyclically accumulated. The cyclicly accumulated samples are examined to find a valid zero crossing. In the event that the aforementioned method does not identify a valid zero crossing, two additional methods for finding a valid zero crossing are employed.

Abstract: A waveform equalizer includes: a data signal input terminal for receiving an input data signal which is the object of waveform equalization; a plurality of S/H circuits each connected to the data signal input terminal; a sampling control circuit for repeatedly bringing the plurality of S/H circuits, one by one, to a sampling operation state; a selection circuit for selecting outputs of a predetermined number of S/H circuits which are in a hold operation state, respectively, from among the plurality of S/H circuits; a weighting circuit for weighting the outputs of the predetermined number of S/H circuits selected by the selection circuit; and an addition circuit for effecting an addition of outputs of the weighting circuit, thereby obtaining a waveform-equalized data signal from an output end of the addition circuit. By the constitution, it is possible to carry out a waveform equalization with high precision, and to realize a high speed of operation and a reduction in the scale of circuit.

Abstract: A signal, in the form of high power, low energy pulses that are generated on cables that are connected directly to the terminals of a low impedance battery, are transmitted between a memory device located on the battery and a data recorder located at the charger end of the battery charging cables. Information transfer between the battery memory device and a charger is done through the battery cables, eliminating the need for special connections. The high power, low energy pulses imposed on the battery cables may be detected at each end of the cables, in spite of the low impedance nature of large lead acid batteries. Pulses are created across the terminals of the battery using a fast acting switch (preferably a FET), a capacitor, and a current limiting resistor connected in series across the cables. When the switch is closed in response to an external command, high power, low energy pulses imposed at one end of the cables are detected at the other end of the cables.

Abstract: Apparatus and method synchronize one or more digital clock signals from separate oscillators, to another clock oscillator via a common non-continuous signal, and provide error signals to indicate when one or more oscillators are out of tolerance.

Abstract: In a method of controlling reproduction of a sampling clock signal, a transmission path clock signal is extracted from the transmission signal. The transmission signal is transmitted with the transmission path clock signal and includes a digital data and a transmission frequency difference data indicative of the difference in frequency between a sampling clock signal and the transmission path clock signal on a transmitting side. The digital data is written in the buffer memory in response to the extracted transmission path clock signal. A start timing of a reproduced sampling clock signal is detected and a phase control signal is generated based on the detected start timing. A reception frequency difference data is produced indicative of a difference in frequency between the extracted transmission path clock signal and the reproduced sampling clock signal such that a frequency control signal is generated based on the transmission frequency difference data and the reception frequency difference data.

Abstract: A redundant clock signal generator which allows the use of differing quantities of oscillators, depending on the degree of reliability desired. Synchronizers accompany each oscillator, and phase detectors monitor the phase deviation between any two oscillators in which synchronization is desired. Multiple pairs of oscillators are synchronized to produce a group of simultaneously synchronized clock signals, which are all concurrently available. Selection circuitry selects a predetermined number of the synchronized clock signals at the request of the selection control circuitry. The selection control circuitry determines which of the synchronized clock signals are to be selected either automatically or through manual intervention. Automatic selection can be triggered upon notification to the selection control circuitry of an error condition.

Abstract: A modulator-demodulator (i.e., modem) permits a personal computer and the like to receive and transmit data in digital format across voice-oriented communications links such as telephone lines. A full-duplex-type modem employs a decoding device decoding the data which are subjected to convolution-encoding operation and amplitude-phase modulation. That data is subjected to amplitude-phase demodulation at first: and then, it is subjected to viterbi decoding by which an error correction is carried out. In the amplitude-phase demodulation, an amplitude-phase plane is employed and is divided into a plurality of areas in accordance with an arrangement of signal-placing points which is used by the amplitude-phase modulation. When receiving the data, a certain receiving point is defined. Then, one of the areas to which the receiving point belongs is determined; and its area information is produced.

Abstract: A radio transceiver comprises a controllable transmitter and receiver, a microprocessor connected to the transmitter and receiver to supply digital data thereto and to receive digital data therefrom, an interface connectable to a keyboard to receive data. The transmitter and receiver, the microprocessor and the interface are enclosed in the housing. Manual controls in the housing control all of the functions of the transmitter and receiver, and the microprocessor can receive inputs from the keyboard to emulate the manual controls.

Abstract: A high-throughput filtering method and corresponding apparatus in which each output sample sn is determined by weighting N input samples xi by multiplying the input samples by N coefficients, where the N coefficients are each decomposed into a set of coordinates, each coordinate corresponding to P bits of the coefficient. Essentially, input samples are multiplied by the coordinates of each of the coefficients in a pre-processing operation where the output signals corresponding to the resulting products for a coefficient are added in an adding block. A plurality of adding blocks are provided corresponding respectively to the coefficients such that each block includes the summation result of the products for a corresponding coefficient. The summation result from a previous adding block is added to the summation result of a current block, and the result of this addition is supplied to the next adding block. The output signal is obtained in this manner.

Abstract: A selective call receiver (10) comprising a processor (108) that couples to a receiver circuit (102), a baud rate detector (106) and a memory device (110). The processor (108) activates the baud rate detector (106) that includes a plurality of registers to perform two baud rate detections to confirm a selective call signal before further processing. When a first baud rate detection detects the selective call signal, the processor (108) combines the results of this first baud rate detection and a plurality of predetermined baud rate parameters to provide a second plurality of predetermined baud rate parameters. The processor (108) then activates the baud rate detector (106) to perform a second baud rate detection using the second plurality of predetermined baud rate parameters. Based on the results of the second baud rate detection, the processor (108) determines whether to continue processing the selective call signal.

Abstract: A variable-length decoder system decodes a variable-length code having different code prefixes in an input bit stream. A code prefix is located in the bit stream and used to determine a number of bits to be selected from the input bit stream according to an access of a code book. Additionally, a pointer, directing access to a different code book, may also be indicated by the access of the first code book according to the located code prefix. A determination is made in this decoder system whether to perform the operation of determining a number of bits to be selected from the input stream or accessing a second code prefix table. If the code value is valid, the number of bits is selected and appended to the code prefix to form a code word which is later decoded by the system of the present invention. If another table is indicated a further code prefix is located in the input stream and the further lookup table is accessed in accordance with the further code prefix.

Abstract: The invention relates to a device for recovering a symbol timing for the decoding of received signals formed by code-modulation symbols transmitted in an orthogonal frequency-division multiplexing mode (OFDM). The signals are formatted in symbol blocks of which each block presents redundant information. The invention comprises means for delaying the symbol blocks and for subtracting from a symbol block the delayed symbol block corresponding thereto. In this manner a difference signal e(t) is obtained which is used for controlling a loop formed by a local oscillator operating at the clock frequency, a frequency divider and a phase comparator.

Abstract: A communication system that reduces significantly the processing required to search over unknown time delays and unknown frequency shifts. Convolutional type processing with a unique re-indexing of the desired signal's Fourier transform is provided so as to allow for the design of a communication system that is invariant to time of arrival and frequency shift such as that caused by doppler effects from moving vehicles or moving satellites. The processing required is several orders of magnitude less computationally intensive than conventional approaches to solving this problem. In addition, the inventive convolutional ambiguity multiple access (CAMA) system can be used in conjunction with M-Ary FSK (Frequency Shift Keying) and other coding techniques to decode the various frequency codes efficiently.

Abstract: At the transmitter side of a signal transmission system, carrier waves are modulated according to an input signal for producing relevant signal points in a signal space diagram. The input signal is divided into two, first and second, data streams. The signal points are divided into signal point groups to which data of the first data stream are assigned. Also, data of the second data stream are assigned to the signal points of each signal point group. A difference in the transmission error rate between the first and second data streams is developed by shifting the signal points to other positions in the space diagram. At the receiver side of a signal transmission, the first and/or second data streams can be reconstructed from a received signal. In TV broadcast service, a TV signal is divided by a transmitter into two, low and high, frequency band components which are designated as a first and a second data stream respectively.

Abstract: A complex angle converter includes a comparing device. The comparing device operates to derive first difference data representing a difference between predetermined reference data and data represented by a first baseband signal. The comparing device further operates to derive second difference data representing a difference between the predetermined reference data and data represented by a second baseband signal having a quadrature relation with the first baseband signal. The comparing device further operates for comparing absolute values of the first difference data and the second difference data, and for outputting a signal representative of a result of the comparing. The complex angle converter also includes a device serving to group an inversion of a highest bit of the first baseband signal and second highest and lower bits of the second baseband signal into a first set.

Abstract: A network node, such as a computer or processing system, is provided, for use within a network, the node including program code for synchronizing a local time maintained at the node with a reference time. Bursts of synchronization messages containing reference time stamps are transmitted over the network, or over a communication link, according to a predetermined protocol. The node receives and time stamps the messages. Thus, times according to a first time scale and a second time scale are obtained. The protocol defines temporal relationships between certain ones of the times. In accordance with the protocol, the node determines a difference between a first time according to one of the time scales and a time related to second and third times according to the other time scale. The node then updates its local time based on the difference.

Abstract: A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

Abstract: There is show a frequency hopping communication system. When a coding circuit 1 informs a spreading code control unit 17 of an error generation, it specifies an erred carrier frequency and counts the errors for each hopping frequency. If the counted errors exceed a fixed value in a frequency, the spreading code control unit 17 changes it to another unused frequency and informs a data communication control unit 14 of changed data. The data communication control unit 14 sends the changed data to the other party apparatus as control data. The other party apparatus receives the control data and recognizes them and changes currently used hopping frequency to a corresponding new one.

Abstract: An adaptive data rate modulator/demodulator (modem) (102), particularly useful for transmitting data over fading communications channels, uses an adaptive data rate technique which supports multiple data rates in the same device. The modem incorporates an adaptive data rate encoder (104) and an adaptive data rate decoder (105) using adaptive, parallel-branch decoding to translate received symbols into corresponding data bits. Significantly, the soft decision metrics of the decoder are also used to provide an estimate W of the signal-to-noise ratio. An optional predictor (232) receives W from the adaptive data rate decoder (105) and predicts the future signal-to-noise ratio to determine the desired data rate for the modem. The data rate is changed automatically and dynamically without interrupting the decoding process. A constant channel symbol rate and a single signal set simplify signal acquisition and synchronization.