Abstract: A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor stacked in that order; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer. The light emitting diode further includes a carbon nanotube layer. The carbon nanotube layer is enclosed in the interior of the first semiconductor layer. The carbon nanotube layer includes a number of carbon nanotubes.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A method and device are provided for forming an integrated Ge or Ge/Si photo detector in the CMOS process by non-selective epitaxial growth of the Ge or Ge/Si. Embodiments include forming an N-well in a Si substrate; forming a transistor or resistor in the Si substrate; forming an ILD over the Si substrate and the transistor or resistor; forming a Si-based dielectric layer on the ILD; forming a poly-Si or a-Si layer on the Si-based dielectric layer; forming a trench in the poly-Si or a-Si layer, the Si-based dielectric layer, the ILD, and the N-well; forming Ge or Ge/Si in the trench; and removing the Ge or Ge/Si, the poly-Si or a-Si layer, and the Si-based dielectric layer down to an upper surface of the ILD. Further aspects include forming an in-situ doped Si cap epilayer or an ex-situ doped poly-Si or a-Si cap layer on the Ge or Ge/Si.

Abstract: An electronic device according to the invention includes: a substrate; an MEMS structure formed above the substrate; and a covering structure defining a cavity in which the MEMS structure is arranged, wherein the covering structure has a first covering layer covering from above the cavity and having a through-hole in communication with the cavity and a second covering layer formed above the first covering layer and closing the through-hole, the first covering layer has a first region located above at least the MEMS structure and a second region located around the first region, the first covering layer is thinner in the first region than in the second region, and a distance between the substrate and the first covering layer in the first region is longer than a distance between the substrate and the first covering layer in the second region.

Abstract: In the disclosed method for manufacturing a semiconductor module, a metal layer and a cooler, which have different coefficients of thermal expansion from each other, are joined into a single unit via an insulating resin sheet. A work, comprising a semiconductor element placed on the metal layer with solder interposed therebetween, is fed into a reflow furnace. The work, in that state, is heated in the reflow furnace, thereby mounting the semiconductor element to the metal layer. The heating is carried out such that the temperature of the cooler and the temperature of the metal layer differ by an amount that make the cooler and the metal layer undergo the same amount of thermal expansion as each other.

Abstract: Various substrates or circuit boards for receiving a semiconductor chip and methods of processing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first opening in a solder mask positioned on a side of a substrate. The first opening does not extend to the side. A second opening is formed in the solder mask that extends to the side. The first opening may serve as an underfill anchor site.

Abstract: An organic light emitting display is disclosed. In one aspect, the display includes a substrate, thin film transistors disposed on the substrate, first, second, and third pixel definition layers disposed on the thin film transistors, respectively having openings, and respectively having first, second, and third heights different from each other, and first, second, and third organic light emitting devices disposed in the openings of the first, second, and third pixel definition layers and connected to the thin film transistors, respectively. The first, second, and third pixel definition layers are spaced apart from each other, the first, second, and third organic light emitting devices have different thicknesses from each other, and the first, second, and third organic light emitting devices have thicknesses respectively corresponding to the first, second, and third heights of the first, second, and third pixel definition layers.

Abstract: A method for producing semiconductor components and a component obtainable by such a method is disclosed. The method comprises the following steps: fixing a conductive film on a carrier; adhesively bonding semiconductor chips onto the conductive film using an adhesive layer, wherein active surfaces of the semiconductor chips, the active surfaces having connection contacts, are situated on that side of the chips which faces the film; overmolding the chips adhesively bonded onto the conductive film with a molding compound; and releasing the conductive film with the overmolded chips from the carrier. In this case, the adhesive layer is structured in such a way that at least connection contacts of the semiconductor chips are free of the adhesive layer and are kept free of the molding compound.

Abstract: An LED package includes an LED die and a lens module. The lens module covers the LED die. Light emitted from the LED die travels through the lens module. The lens module includes a concave lens and a convex lens with a smaller radial dimension than that of the concave lens. The concave lens covers the LED die. The convex lens is attached on a center of a surface of the concave lens away from the LED die. Optical axes of the concave lens and the convex lens are both collinear with a central axis of the LED die. Light from the LED die is diverged by the lens module to a peripheral side of the LED package.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units.

Abstract: A method for fabricating a high voltage semiconductor device is provided. Firstly, a substrate is provided, wherein the substrate has a first active zone and a second active zone. Then, a first ion implantation process is performed to dope the substrate by a first mask layer, thereby forming a first-polarity doped region at the two ends of the first active zone and a periphery of the second active zone. After the first mask layer is removed, a second ion implantation process is performed to dope the substrate by a second mask layer, thereby forming a second-polarity doped region at the two ends of the second active zone and a periphery of the first active zone. After the second mask layer is removed, a first gate conductor structure and a second gate conductor structure are formed over the middle segments of the first active zone and the second active zone, respectively.

Abstract: In a semiconductor diamond device, there is provided an ohmic electrode that is chemically and thermally stable and has an excellent low contact resistance and high heat resistance. A nickel-chromium alloy, or a nickel-chromium compound, containing Ni and Cr such as Ni6Cr2 or Ni72Cr18Si10, which is chemically and thermally stable, is formed on a semiconductor diamond by a sputtering process and so forth, to thereby obtain the semiconductor diamond device provided with an excellent ohmic electrode. If heat treatment is applied after forming the nickel-chromium alloy or compound, it is improved in characteristics.

Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.

Abstract: A device includes a first switch and a second switch, each switch being integrated on a chip having a back surface and an opposite front surface. Each chip includes a first conduction terminal and a control terminal on the front surface, while a second conduction terminal of the switch is located on the back surface. The first switch and the second switch are connected in a half-bridge configuration with the first switch's second conduction terminal electrically connected to the second switch's first conduction terminal. The chips are installed in a common package comprising an insulating body with an embedded heat sink. The chips of the switches are mounted on the heat sink such that the second conduction terminal of the first switch and the first conduction terminal of the second switch are in contact with the heat sink, with the heat sink providing the electrical connection between the two switches.

Abstract: A power MOSFET includes an epitaxy substrate, conductive trenches, well regions and a dielectric layer. The power MOSFET further has at least one termination structure including at lest one of the conductive trenches, some of the well regions within a termination area and mutually insulated by the conductive trench, a field plate, a contact plug and a heavily-doped region. The field plate including a plate metal and the dielectric layer is on the well regions and the conductive trench within the termination area. The contact plug penetrates through the dielectric layer and connects the plate metal and one of the well regions, so the plate metal has equal potential with the connected well region through the contact plug. The well regions and the conductive trench are electrically coupled to the plate metal by the dielectric layer. The heavily-doped region is between the contact plug and the connected well region.

Abstract: Embodiments of the present invention provided a method of fabricating a semiconductor light source structure. The method comprises providing a GaAs substrate; forming a lower cladding layer above the substrate, the lower cladding layer comprising an AIxGa1-xAs alloy; forming an active region above the lower cladding layer, the active region comprising a GaAs separate confinement heterostructure; and forming an upper cladding layer comprising an AIxGa1-xAs alloy above the active region in the form of an elongate stripe bounded on either side by an InGaP current-blocking layer, the elongate stripe defining an index-guided optical waveguide.

Abstract: A semiconductor light detecting element includes: an InP substrate; and a semiconductor stacked structure on the InP substrate and including at least a light absorbing layer, wherein the light absorbing layer includes an InGaAsBi layer lattice-matched to the InP substrate.

Abstract: When forming sophisticated semiconductor devices, three-dimensional transistors in combination with planar transistors may be formed on the basis of a replacement gate approach and self-aligned contact elements by forming the semiconductor fins in an early manufacturing stage, i.e., upon forming shallow trench isolations, wherein the final electrically effective height of the semiconductor fins may be adjusted after the provision of self-aligned contact elements and during the replacement gate approach.

Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

Abstract: The present invention is a solar cell 500 comprising the substrate 510 made of a crystalline semiconductor, an i-type semiconductor layer 520a and an i-type semiconductor layer 520b each made of an amorphous semiconductor, and a first-conductivity type semiconductor layer 530 and a second-conductivity type semiconductor layer 540 each made of an amorphous semiconductor, in which by catalytic chemical vapor deposition in which catalyzers decompose raw gas when being heated by receiving an electric current, the i-type semiconductor layer 520a is formed on the principle plane 515a by the catalyzer placed at the position facing the principle plane 515a, the i-type semiconductor layer 520b is formed on the principle plane 515b by the catalyzer placed at the position facing the principle plane 515b are formed on the i-type semiconductor layer 520a and the i-type semiconductor layer 520b on the substrate 510.