Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

Abstract: A light emitting diode includes a substrate, a first semiconductor layer, an active layer and a second semiconductor layer. The first semiconductor layer, the active layer and the second semiconductor layer are stacked on one side of the substrate in that order. The first semiconductor layer is oriented to the substrate. A number of channels are defined between the first semiconductor layer and the substrate.

Abstract: An embodiment of the invention provides a pixel structure of an active matrix organic light emitting display comprising a gate line, a common electrode line, a signal line, a power line, a first thin film transistor which is used as an addressing element, and a second thin film transistor which controls the organic light emitting display. A short-circuit-ring structure is connected between the common electrode line and the signal line and the short-circuit-ring structure communicates the signal line and the common electrode line in the case where a large current flows.

Abstract: A mechanically improved component comprising a chip in a cavity and a stress-reduced attachment is specified. A component comprises an opening in a housing, an opaque cover or a mechanically flexible line connector, which is attached to two locations.

Abstract: A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.

Abstract: A semiconductor device includes a semiconductor chip coupled to a substrate and a base plate coupled to the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure.

Abstract: An ion sensitive sensor having an EIS structure, including: a semiconductor substrate, on which a layer of a substrate oxides is produced; an adapting or matching layer, which is prepared on the substrate oxide; a chemically stable, intermediate insulator, which is deposited on the adapting or matching layer; and an ion sensitive, sensor layer, which is applied on the intermediate insulator. The adapting or matching layer differs from the intermediate insulator and the substrate oxide in its chemical composition and/or structure. The adapting or matching layer and the ion sensitive, sensor layer each have an electrical conductivity greater than that of the intermediate insulator. There is an electrically conductive connection between the adapting or matching layer and the ion sensitive, sensor layer.

Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.

Abstract: A light emitting diode package comprises a light emitting diode chip, a first luminescent conversion layer and a separate second luminescent conversion layer on the first luminescent conversion layer. The first luminescent conversion layer has a first luminescent conversion element surrounding the light emitting diode chip. The second luminescent conversion layer has a second luminescent conversion element located above the light emitting diode chip. An excitation efficiency of the first luminescent conversion element is higher than that of the second luminescent conversion element.

Abstract: Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.

Abstract: A miniature packaging for a discrete circuit component that comprises a core dice for the circuit component fabricated on a semiconductor substrate. The core dice has at least a pair of metallization electrodes formed on the same or different surfaces of the semiconductor substrate. An end electrode covers a corresponding side surface of the core dice and electrically connects to a corresponding one of the pair of metallization electrodes. The end electrode extends toward the center of the core dice on both the top and bottom surface of the core dice.

Abstract: A method of manufacturing a thin film electronic device comprises applying a first plastic coating (PI-1) directly to a rigid carrier substrate (40) and forming thin film electronic elements (44) over the first plastic coating. A second plastic coating (46) is applied over the thin film electronic elements with electrodes (47) on top, with a portion lying directly over the associated electronic element, spaced by the second plastic coating. The rigid carrier substrate (40) is released from the first plastic coating, by a laser release process. This method enables traditional materials to be used as the base for the electronic element manufacture, for example thin film transistors. The second plastic coating can form part of the known field shielded pixel (FSP) technology.

Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.

Abstract: Provided is an organic electronic panel wherein warping (deformation) of a metal member is suppressed when the metal member is used as a packaging board, an electrical short-circuit due to the warping is eliminated, and generation of light emission failure and deterioration of power generating performance are eliminated. In the organic electronic panel, the packaging board is composed of a metal foil, and a polymer film is laminated on the metal foil surface on the reverse side of the side having the adhesive layer. The thickness of the polymer film is not more than that of the metal foil, and heat is applied at the time of bonding/laminating the packaging board or at the time of hardening the adhesive layer.

Abstract: An objective is to provide a semiconductor device capable of utilizing properties of a high-mobility electron transport layer with a thin film stacked structure having large ?Ec, high electron mobility, and simplified element fabrication process even when the substrate material and the electron transport layer greatly differ in lattice constant. The semiconductor device includes: a semiconductor substrate (1); a first barrier layer (2) on the substrate (1); an electron transport layer (3) on the first barrier layer (2); and a second barrier layer (4) on the electron transport layer (3). The first barrier layer (2) has an InxAl1-xAs layer. At least one of the first barrier layer (2) and the second barrier layer (4) has a stacked structure having an AlyGa1-yAszSb1-z layer in contact with the electron transport layer (3) and an InxAl1-xAs layer in contact with the AlyGa1-yAszSb1-z layer. The stacked structure is doped with a donor impurity.

Abstract: A substrate achieving suppressed deterioration of processing accuracy of a semiconductor device due to bending of the substrate, a substrate with a thin film and a semiconductor device formed with the substrate above, and a method of manufacturing the semiconductor device above are obtained. A substrate according to the present invention has a main surface having a diameter of 2 inches or greater, a value for bow at the main surface being not smaller than ?40 ?m and not greater than ?5 ?m, and a value for warp at the main surface being not smaller than 5 ?m and not greater than 40 ?m. Preferably, a value for surface roughness Ra of the main surface of the substrate is not greater than 1 nm and a value for surface roughness Ra of a main surface is not greater than 100 nm.

Abstract: An ESD protection device includes a ceramic multilayer substrate, at least one pair of discharge electrodes provided in the ceramic multilayer substrate and facing each other with a space formed therebetween, external electrodes provided on a surface of the ceramic multilayer substrate and connected to the discharge electrodes. The ESD protection device includes a supporting electrode obtained by dispersing a metal material and a semiconductor material and being arranged in a region that connects the pair of discharge electrodes to each other.

Abstract: A double gate thin-film transistor (TFT), and an organic light-emitting diode (OLED) display apparatus including the double gate TFT, includes a double gate thin-film transistor (TFT) including: a first gate electrode on a substrate; an active layer on the first gate electrode; source and drain electrodes on the active layer; a planarization layer on the substrate and the source and drain electrodes, and having an opening corresponding to the active layer; and a second gate electrode in the opening.