Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.

Abstract: An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board.

Abstract: The disclosed semiconductor light-emitting element is configured from layering an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer (160); and a first electrode (200), which is the cathode, is formed on the p-type semiconductor layer (160). Also, between the p-type semiconductor layer (160) and a reflecting layer (220b), the first electrode (200) is provided with a crystalline first transparent electrode layer (210) and a non-crystalline second transparent electrode layer (220a). The crystalline first transparent electrode layer (210) increases adhesion with the p-type semiconductor layer (160), and the non-crystalline second transparent electrode layer (220a) suppresses delamination of the reflecting layer (220b). Also, the first transparent electrode layer (210) and the second transparent electrode layer (220a) transmit light emitted from the light-emitting layer and suppress degradation of reflective characteristics.

Abstract: Disclosed are a light emitting device and a light emitting device package having the same. The light emitting device includes a first chip structure including a first reflective layer and a first light emitting structure having a plurality of compound semiconductor layers on the first reflective layer; a second chip structure bonded onto the first chip structure and including a second reflective layer and a second light emitting structure having a plurality of compound semiconductor layers on the second reflective layer; and an electrode on the second chip structure.

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract: A semiconductor structure having an in situ chip-level ferrite bead inductor and method for forming the same. Embodiments include a substrate, a first dielectric layer formed on the substrate, a lower ferrite layer formed on the first dielectric layer, and an upper ferrite layer spaced apart from the lower ferrite layer in the structure. A first metal layer may be formed above the lower ferrite layer and a second metal layer formed below the upper ferrite layer, wherein at least the first or second metal layer has a coil configuration including multiple turns. At least one second dielectric layer may be disposed between the first and second metal layers. The ferrite bead inductor has a small form factor and is amenable to formation using BEOL processes.

Abstract: A wide-band-gap reverse-blocking MOS-type semiconductor device includes a SiC n?-type drift layer; a p+-type substrate on the first major surface side of the drift layer; a trench extending through a p+-type substrate into the drift layer; a titanium electrode in the trench bottom that forms a Schottky junction with the SiC n?-type drift layer; an active section including a MOS-gate structure on the second major surface side of the drift layer facing to the area, in which the Schottky junctions are formed; a breakdown withstanding section surrounding the active section; and a trench isolation layer surrounding the breakdown withstanding section, the trench isolation layer extending from the second major surface of the drift layer into p+-type substrate and including insulator film buried therein. The device facilitates making a high current flow with a low ON-voltage and exhibits a very reliable reverse blocking capability.

Abstract: A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.

Abstract: Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Abstract: Provided is a semiconductor device including a wiring board having a first surface on which a board-side ground terminal and a board-side power supply terminal are provided; a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip; a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface; a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal; a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other.

Abstract: An LED light module free of jumper wires has a substrate and multiple LED chips. The substrate has a positive side circuit, a negative side circuit, multiple first chip connection portions and multiple second connection portions. The first and second chip connection portions are respectively connected to the positive and negative side circuits, and are juxtaposedly and alternately arranged on the substrate so that a width between each first chip connection portion and a corresponding second chip connection portion is smaller than a width of each LED chip. Each LED chip can be directly mounted on corresponding first and second chip connection portions to electrically connect to the positive and negative side circuits. Accordingly, jumper wires for connecting the LED chips and the positive and negative side circuits can be removed to avoid broken jumper wires occurring when the LED light module is shipped or assembled.

Abstract: A sensor for detecting intensity of radiation such as of infrared radiation includes an ROIC substrate (9) and a resistance element (1) arranged at a distance of the surface of the ROIC substrate. The resistance element comprises one more semiconducting layers such as a silicon semiconducting layer and a semiconducting layer of a silicon-germanium alloy forming a heterojunction. The semiconducting layer or layers can be doped with one or more impurity dopants, the doping level or levels selected so that the layer retains the basic crystallographic properties of the respective material such as those of monosilicon or a monocrystalline silicon-germanium alloy. The impurity dopants are selected from the elements in groups IE, IV, and V, in particular among boron, aluminium, indium, arsenic, phosphorous, antimony, germanium, carbon and tin. The doping can be abrupt so that there is an interior layer inside said semiconducting layer or layers having a significantly higher doping level.

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract: A light emitting diode includes a first semiconductor layer, an active layer and a second semiconductor layer stacked in that order; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the second semiconductor layer. The light emitting diode further includes a carbon nanotube layer. The carbon nanotube layer is enclosed in the interior of the first semiconductor layer. The carbon nanotube layer includes a number of carbon nanotubes.

Abstract: An LED package includes a substrate, a transparent base, an LED chip and a reflective layer. The substrate has an upper surface. The transparent base is arranged on the upper surface of the substrate. The transparent base includes a first surface away from the substrate and a second surface opposite to the first surface. The LED chip is arranged on the first surface of the transparent base. The reflective layer is arranged between the substrate and the second surface of the transparent base.

Abstract: An LED package comprises a substrate, a reflector, a light-absorbing layer, an encapsulation layer and an LED chip. The light-absorbing layer is located around the reflector and is able to absorb any light which penetrates through the reflector. Therefore, any vignetting or halation of light from the LED package is prevented. Moreover, the LED package can be constructed on a very small scale with no reduction in its color rendering properties.

Abstract: A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.

Abstract: A light emitting diode includes a substrate, a carbon nanotube layer, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked on one side of the substrate in that order. The first semiconductor layer is adjacent to the substrate. The carbon nanotube layer is located between the first semiconductor layer and the substrate. The first electrode is electrically connected to the first semiconductor layer. The second electrode is electrically connected to the second semiconductor layer.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A solid-state imaging device includes a photoelectric conversion unit that is formed on a semiconductor substrate, a reading unit that reads signal charges of the photoelectric conversion unit, a gate insulating film and an electrode disposed thereon that constitute the reading unit, a light shielding film that covers the electrode, and an antireflection film that is formed on the photoelectric conversion unit and is constituted by films of four or more layers. The film of the lower layer of the antireflection film is also used as a stopper film during patterning, and a gap between the end of the light shielding film and the semiconductor substrate which is defined by interposing a plurality of films of the lower layer of the antireflection film is set so as to be smaller than the thickness of the gate insulating film.