Abstract: A lighting emitting device includes a conductive substrate; a first conductive layer formed on the conductive substrate; a second conductive layer formed on the first conductive layer; a second semiconductor layer formed on the second conductive layer; an active layer formed on the second semiconductor layer; a first semiconductor layer being formed on the active layer and including a charge distribution layer; and an insulation layer.
Abstract: A LED package structure includes a substrate, a LED chip and a colloid. The substrate includes a first surface and a second surface. An opening is shaped from the first surface toward the second surface. A phosphor layer is coated on the bottom surface with two opposite parts of the bottom surface respectively neighboring to two opposite side walls of the opening exposed. A metal layer is coated on the two exposed opposite parts of the bottom surface, the two opposite side walls and the first surface. The LED chip is received in the opening and configured on the phosphor layer. The LED chip includes a pair of conductive pads electrically connecting to the metal layer. The colloid is filled between the LED chip and the metal layer to attach the substrate to the LED chip.
Type:
Grant
Filed:
June 1, 2011
Date of Patent:
February 19, 2013
Assignees:
Ambit Microsystems (Zhongshan) Ltd., Hon Hai Precision Industry Co., Ltd.
Abstract: A semiconductor device comprises a substrate including a first region and a second region of a first conductivity type and a third region between the first and second regions of a second conductivity type opposite to the first conductivity type, and being covered by a dielectric layer. A plurality of trenches laterally extend between the third and second region, are filled with an insulating material, and are separated by active stripes with a doping profile having a depth not exceeding the depth of the trenches wherein each trench terminates before reaching the dielectric layer and is separated from the third region by a substrate portion such that the respective boundaries between the substrate portions and the trenches are not covered by the dielectric layer. A method for manufacturing such a semiconductor device is also disclosed.
Abstract: The embodiments of the present invention disclose a semiconductor device and a method for forming the semiconductor device. Wherein the semiconductor comprises: a first semiconductor layer, having a first conductivity type on a semiconductor substrate, a guard ring region, formed in the surface of the first semiconductor layer, having a second conductivity type; a Schottky diode metal contact, coupled to the first semiconductor layer, wherein the guard ring region is at periphery of the Schottky diode interface, and wherein the Schottky diode metal contact has no direct electrical connection with the guard ring region; and an electrical resistance module, coupled between the Schottky diode metal contact and the guard ring. Due to the ballasting effect from the electrical resistance module, the minority injection or the parasitic transistor action are alleviated. Thus, forward current capability is extended without introducing significant minority injection.
Abstract: A semiconductor structure includes a substrate, a thermally and electrically conductive mask positioned upon the substrate, and an epitaxial lateral over growth (ELOG) material positioned upon the thermally and electrically conductive mask.
Type:
Grant
Filed:
December 16, 2008
Date of Patent:
February 5, 2013
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Shih-Yuan Wang, Lars Helge Thylen, Sagi Varghese Mathai
Abstract: Provided are a multi-chip package and a method of manufacturing the same, which can facilitate wire bonding even when an upper chip is larger than a lower chip or overhangs a lower chip. A multi-chip package includes a substrate having first and second bonding pads on a top surface thereof, a first chip connected to the first bonding pads on the substrate, an insulating layer formed on the substrate so as to surround lateral surfaces of the first chip, a set of openings formed in the insulating layer so as to expose the second bonding pads, and a second chip formed on the insulating layer and the first chip, the second chip having a larger area than the first chip and connected to the second bonding pads using wires that pass through the second openings.
Abstract: An exemplary light emitting diode (LED) package includes a substrate, an LED chip mounted on the substrate, and a wire. The LED chip includes a semiconductor structure and an electrode disposed on the semiconductor structure. The wire electrically connects the electrode of the LED chip to an electrical portion of the substrate. The wire has a first joint and a second joint connected to the substrate. The wire forms a first curved portion between the electrode and the first joint and a second curved portion between the first joint and the second joint.
Type:
Grant
Filed:
May 31, 2011
Date of Patent:
January 1, 2013
Assignee:
Advanced Optoelectronic Technology, Inc.
Abstract: A thin-film semiconductor device includes, in order, a substrate, a gate electrode, a gate insulating film, a first channel layer, and a second channel layer. The second channel layer includes a protrusion between first top surface end portions. The protrusion has first lateral surfaces that each extend between one of the first top surface end portions and a top surface of the protrusion. An insulation layer is on the top surface of the protrusion. The insulation layer has second lateral surfaces that each extend to one of second top surface end portions of the insulation layer. Two contact layers are each on one of the second top surface end portions of the insulation layer, adjacent one of the second lateral surfaces of the insulation layer, adjacent one of the first lateral surfaces of the protrusion, and on one of the first top surface end portions of the second channel layer. A source electrode is on one of the two contact layers, and a drain electrode is on the other of the two contact layers.