Abstract: A semiconductor package includes a first device, a second device and a solder region. The first device includes a first conductive pillar, wherein the first conductive pillar has a first sidewall, a second sidewall opposite to the first sidewall, a first surface and a second surface physically connected to the first surface, the first surface and the second surface are disposed between the first sidewall and the second sidewall, and an included angle is formed between the first surface and the second surface. The solder region is disposed between the first conductive pillar and the second device to bond the first device and the second device.

Abstract: According to at least one aspect, a lighting device is provided. The lighting device comprises a circuit board; a light emitting diode (LED) array mounted to the circuit board and configured to emit broad spectrum light at any one of a plurality of different color correlated temperature (CCT) values within a range of CCT values, the LED array comprising a first LED configured to emit narrow spectrum light and a second LED that is different from the first LED and configured to emit broad spectrum light; and at least one elastomer encapsulating at least part of the circuit board and the LED array mounted to the circuit board.

Abstract: A current sensor package, comprises a current path and a sensing device. The sensing device is spaced from the current path, and the sensing device is configured for sensing a magnetic field generated by a current flowing through the current path. Further, the sensing device comprises a sensor element. The sensing device is electrically connected to a conductive trace. An encapsulant extends continuously between the current path and the sensing device.

Abstract: Provided are an imaging apparatus and an electronic device in which even if an image sensor is mounted on a wiring board, the wiring board on which the image sensor is mounted can be assembled to a housing with high accuracy. Provided is an imaging apparatus including a sensor chip and a wiring board having a glass base material. The imaging apparatus is joined to at least one of the sensor chip or the wiring board via a bump unit including a plurality of bumps, and each of the plurality of bumps is formed by conductive members having substantially the same composition.

Abstract: A wiring design method and a wiring structure for a package substrate in a flip chip, and a flip chip. The wiring design method includes: arranging bump pads in an array of rows and columns, wherein the bump pads are configured to bond with conductive bumps on a flip chip die, and the bump pads comprise signal pads and non-signal pads; providing the non-signal pad with a via hole; and using a layer of wiring to lead a subset of the signal pads out of an orthographic projection region of the flip chip die on the package substrate, wherein the subset of the signal pads is configured to carry all functional signals required by design specifications of the flip chip die for the array of the bump pads.

Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

Abstract: The present disclosure provides a flexible substrate, the flexible substrate is divided into a display region, a binding region on a side of the display region, a to-be-bent region between the display region and the binding region, two transition regions between the to-be-bent region and the display region and between the to-be-bent region and the binding region respectively; the transition regions comprise a plurality of transition sub-regions arranged in a first direction, the first direction is a direction from the display region to the binding region; the flexible substrate comprises a flexible base and a back film disposed on the flexible base, a portion of the back film is located in the transition regions; in any one of the transition regions, the amount of distribution per unit area of the back film in each of the transition sub-regions gradually decreases in a direction gradually approaching the to-be-bent region.

Abstract: A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.

Abstract: The present disclosure provides an OLED display panel, a preparation method thereof and an OLED display device. By providing an uneven surface on a side of a first encapsulation layer away from the organic light-emitting function layer in a non-display area, the uneven surface of the first encapsulation layer can block the flow of the second encapsulation layer to a certain extent, so as to reduce the fluidity and the climbing distance of the edge of the second encapsulation layer, and increase the edge stress and the slope angle. Thereby the narrow frame design of the product is achieved, the thickness uniformity of the edge of the second encapsulation layer is improved, the Mura defect in the non-display area is avoided, and the encapsulation result is guaranteed.

Abstract: A package and a method of forming the same are provided. A method includes forming a first die structure. The first die structure includes a die stack and a stacked dummy structure bonded to a carrier. A second die structure is formed. The second die structure includes a first integrated circuit die. The first die structure is bonded to the second die structure by bonding a topmost integrated circuit die of the die stack to the first integrated circuit die. The topmost integrated circuit die of the die stack is a farthest integrated circuit die of the die stack from the carrier. A singulation process is performed on the first die structure to form a plurality of individual die structures. The singulation process singulates the stacked dummy structure into a plurality of individual stacked dummy structures.

Abstract: Embodiments of the present disclosure provide an integrated circuit die with vertical interconnect features to enable direct connection between vertically stacked integrated circuit dies. The vertical interconnect features may be formed in a sealing ring, which allows higher routing density than interposers or redistribution layer. The direct connection between vertically stacked integrated circuit dies reduces interposer layers, redistribution process, and bumping processes in multi-die integration, thus, reducing cost of manufacturing.

Abstract: A display module includes a display panel for displaying an image, and a protective film adhered to a back surface of the display panel. The protective film includes a compensation layer being in contact with the back surface of the display panel, a first release layer disposed under the compensation layer, a cushion layer disposed under the first release layer, and a second release layer disposed under the cushion layer. An adhesive strength of the first release layer is less than an adhesive strength of the second release layer.

Abstract: The present disclosure relates to a flexible display substrate and a method of manufacturing the same, a display panel and a display apparatus. The flexible display substrate has a display region and a non-display region. In some embodiments, the flexible display substrate comprises: a base substrate and an inorganic film layer provided on the base substrate, wherein the inorganic film layer of the non-display region is provided with a groove; and a filling structure for filling the groove.

Abstract: The aim is to improve the bending resistance a display device. The display device in one embodiment includes a substrate including a first surface and a second surface and a curved part between the first surface and the second surface, a display element arranged on the first surface, a conducting layer connected with the display element and extending to the second surface from the first surface via the curved part, a plurality of protective layers having a lower ductility than the substrate and arranged in the substrate side and/or opposite side to the substrate side with respect to the conducting layer and along the curved part, wherein each of the plurality of protective layers spreading over the curved part, to a certain region of the first surface side from the curved part, and to a certain region of the second side from the curved part.

Abstract: A semiconductor device includes a semiconductor die with a metallization layer including a first metal with a comparatively high melting point, a die carrier including a second metal with a comparatively high melting point, a first intermetallic compound arranged between the semiconductor die and the die carrier and including the first metal and a third metal with a comparatively low melting point, a second intermetallic compound arranged between the first intermetallic compound and the die carrier and including the second metal and the third metal, and precipitates of a third intermetallic compound arranged between the first intermetallic compound and the second intermetallic compound and including the third metal and a fourth metal with a comparatively high melting point.

Abstract: An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.

Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.

Abstract: Techniques for a quantum device with modular quantum building blocks are provided. In one embodiment, a device is provided that comprises a substrate that is coupled with a plurality of qubit pockets, where at least one qubit pocket of the plurality of qubit pockets is coupled with a qubit. In one implementation, the device can further comprise a plurality of connectors coupled to the substrate and positioned around at least a portion of the substrate, where the plurality of connectors comprising a connecting element. In one or more implementations, the device can further comprise a plurality of transmission lines formed on the substrate and connect at least one connector of the plurality of connectors to at least one qubit pocket of the plurality of qubit pockets.

Abstract: A multi-chip integrated circuit (IC) apparatus includes a substrate, one or more first IC chips mounted on the substrate, and a second IC chip mounted on the substrate. One or more first heat sinks are respectively thermally coupled to the one or more first IC chips. A second heat sink is thermally coupled to the second IC chip. An under side of the second heat sink is located further from the substrate than each of respective one or more top sides of the one or more first heat sinks.

Abstract: The present disclosure relates to an electronic display device, including a rigid substrate including a first surface, a second surface opposite the first surface, and a side surface coupled between the first surface and the second surface, a flexible OLED layer including a first body segment extending over the first surface of the rigid substrate to form a display front surface of the electronic display device, a second body segment extending over the second surface of the rigid substrate to form a back surface of the electronic display device, and a bent segment coupled between the first body segment and the second body segment, and a functional component coupled to the second body segment of the flexible OLED layer to implement a display function of the electronic display device, the functional component being hidden on the back surface of the electronic display device.