Patents Examined by Hung K. Vu
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Patent number: 11694977Abstract: In an embodiment a method includes providing the first component part with a partially exposed first insulating layer, a plurality of first through-vias and an exposed first contact layer structured in places and planarized in places, wherein the first through-vias are each laterally enclosed by the first insulating layer, and wherein the first contact layer partially covers the first insulating layer and completely covers the first through-vias; providing the second component part with a partially exposed second insulating layer, a plurality of second through-vias and an exposed second contact layer structured in places and planarized in places, wherein the second through-vias are each laterally enclosed by the second insulating layer, and wherein the second contact layer partially covers the second insulating layer and completely covers the second through-vias and joining the component parts such that the contact layers overlap each other thereby mechanically and electrically connecting the component partsType: GrantFiled: May 8, 2019Date of Patent: July 4, 2023Assignee: OSRAM Opto Semiconductors GmbHInventors: Simeon Katz, Sophia Huppmann, Michael Hoenle, Thorsten Wagner, Kurt Hingerl
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Patent number: 11682614Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.Type: GrantFiled: November 12, 2021Date of Patent: June 20, 2023Assignee: SK hynix Inc.Inventors: Hyun Chul Seo, Jun Sik Kim
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Patent number: 11676926Abstract: A method for interconnecting two conductors includes creating a first nickel layer on a first conductor of an electrical component, producing a first non-gold protective layer on the first nickel layer, the first non-gold protective layer being configured to prevent the first nickel layer from oxidizing, creating a second nickel layer on a second conductor, producing a second non-gold protective layer on the second nickel layer, the second non-gold protective layer being configured to prevent the second nickel layer from oxidizing, and interconnecting the first and second nickel layers using a solder layer that interfaces with the first and second nickel layers between the first and second conductors.Type: GrantFiled: August 24, 2020Date of Patent: June 13, 2023Assignee: Schlumberger Technology CorporationInventors: Mark Alex Kostinovsky, Steven O. Dunford, Lweness Mazari
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Patent number: 11670533Abstract: An exemplary wafer structure comprises a source wafer having a patterned sacrificial layer defining anchor portions separating sacrificial portions. A patterned device layer is disposed on or over the patterned sacrificial layer, forming a device anchor on each of the anchor portions. One or more devices are disposed in the patterned device layer, each device disposed entirely over a corresponding one of the one or more sacrificial portions and spatially separated from the one or more device anchors. A tether structure connects each device to a device anchor. The tether structure comprises a tether device portion disposed on or over the device, a tether anchor portion disposed on or over the device anchor, and a tether connecting the tether device portion to the tether anchor portion. The tether is disposed at least partly in the patterned device layer between the device and the device anchor.Type: GrantFiled: July 6, 2020Date of Patent: June 6, 2023Assignee: X Display Company Technology LimitedInventors: Christopher Andrew Bower, Matthew Meitl, Salvatore Bonafede, Brook Raymond, Carl Ray Prevatte, Jr.
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Patent number: 11670575Abstract: A package structure, and a RDL structure are provided. The package structure incudes a die and a RDL structure electrically connected to the die. The RDL structure includes a first redistribution layer, a second redistribution layer and a third redistribution layer. The first redistribution layer includes a first ground plate. The second redistribution layer includes a second ground plate and a signal trace. The signal trace is laterally spaced from the second ground plate. The third redistribution layer includes a third ground plate. The third redistribution layer and the first redistribution layer are disposed on opposite sides of the second redistribution layer. The signal trace is staggered with at least one of the first ground plate and the third ground plate in a direction perpendicular to a top surface of the signal trace.Type: GrantFiled: August 5, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Hsun Chen, Jiun-Yi Wu, Shou-Yi Wang
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Patent number: 11664308Abstract: A semiconductor device includes: a first conductive structure having sidewalls and a bottom surface, the first conductive structure extending through one or more isolation layers formed on a substrate; and an insulation layer disposed between at least one of the sidewalls of the first conductive structure and respective sidewalls of the one or more isolation layers, wherein the first conductive structure is electrically coupled to a second conductive structure through at least the bottom surface.Type: GrantFiled: January 22, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Liang Cheng, Shih Wei Bih, Yen-Yu Chen
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Patent number: 11652030Abstract: Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.Type: GrantFiled: December 29, 2020Date of Patent: May 16, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jonghwan Baek, JeongHyuk Park, Seungwon Im, Keunhyuk Lee
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Patent number: 11646282Abstract: A bonded assembly includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes first metallic bonding pads embedded in first dielectric material layers, the second semiconductor die includes second metallic bonding pads embedded in second dielectric material layers, the first metallic bonding pads are bonded to a respective one of the second metallic bonding pads; and each of the first metallic bonding pads includes a corrosion barrier layer containing an alloy of a primary bonding metal and at least one corrosion-suppressing element that is different from the primary bonding metal.Type: GrantFiled: February 4, 2021Date of Patent: May 9, 2023Assignee: SANDISK TECHNOLOGIES LLCInventors: Lin Hou, Peter Rabkin, Masaaki Higashitani
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Patent number: 11640935Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.Type: GrantFiled: July 16, 2021Date of Patent: May 2, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
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Patent number: 11640986Abstract: A semiconductor device, and a method of manufacturing, is provided. A dummy gate is formed on a semiconductor substrate. An interlayer dielectric (ILD) is formed over the semiconductor fin. A dopant is implanted into the ILD. The dummy gate is removed and an anneal is performed on the ILD. The implantation and the anneal lead to an enhancement of channel resistance by a reduction in interlayer dielectric thickness and to an enlargement of critical dimensions of a metal gate.Type: GrantFiled: June 30, 2021Date of Patent: May 2, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chang Lin, Tien-Shun Chang, Szu-Ying Chen, Chun-Feng Nieh, Sen-Hong Syue, Huicheng Chang
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Patent number: 11637083Abstract: In a described example, a method includes: forming cavities in a die mount surface of a package substrate, the cavities extending into the die mount surface of the package substrate at locations corresponding to post connects on a semiconductor die to be flip-chip mounted to the package substrate; placing flux in the cavities; placing solder balls on the flux; and performing a thermal reflow process and melting the solder balls to form solder pads in the cavities on the package substrate.Type: GrantFiled: March 31, 2021Date of Patent: April 25, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Rafael Jose Lizares Guevara, John Carlo Cruz Molina, Steffany Ann Lacierda Moreno
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Patent number: 11631771Abstract: An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor.Type: GrantFiled: July 6, 2021Date of Patent: April 18, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chien-Ming Lai, Yen-Chen Chen, Jen-Po Huang, Sheng-Yao Huang, Hui-Ling Chen, Qinggang Xing, Ding-Lung Chen, Li Li Ding, Yao-Hung Liu
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Patent number: 11626525Abstract: A package structure is provided. The package structure includes a substrate, a sensor device, an encapsulant and a signal blocking structure. The substrate has a signal passing area. The sensor device is disposed over the substrate. The sensor device has a first surface, a second surface opposite to the first surface and a sensing area located at the second surface. The second surface of the sensor device faces the substrate. The encapsulant covers the sensor device and the substrate. The signal blocking structure extends from the substrate into the encapsulant.Type: GrantFiled: September 4, 2020Date of Patent: April 11, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun Yu Ko, Tsu-Hsiu Wu, Meng-Jen Wang
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Patent number: 11626394Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.Type: GrantFiled: February 25, 2021Date of Patent: April 11, 2023Assignee: KIOXIA CORPORATIONInventors: Akihiko Chiba, Takahiro Tsurudo, Kenichi Matoba, Yoshifumi Shimamura, Hiroaki Nakasa, Hiroyuki Takenaka
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Patent number: 11626370Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.Type: GrantFiled: March 25, 2021Date of Patent: April 11, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Keumhee Ma, Chulyong Jang
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Patent number: 11621296Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.Type: GrantFiled: April 6, 2021Date of Patent: April 4, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kun-Ju Li, Tai-Cheng Hou, Hsin-Jung Liu, Fu-Yu Tsai, Bin-Siang Tsai, Chau-Chung Hou, Yu-Lung Shih, Ang Chan, Chih-Yueh Li, Chun-Tsen Lu
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Patent number: 11605736Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.Type: GrantFiled: June 21, 2021Date of Patent: March 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 11594419Abstract: A method for reducing wiggling in a line includes forming a silicon patterning layer over a substrate and depositing a mask layer over the silicon patterning layer. The mask layer is patterned to form one or more openings therein. The mask layer is thinned and the one or more openings are widened, to provide a smaller height-to-width ratio. The pattern of the mask layer is then used to pattern the silicon patterning layer. The silicon patterning layer is used, in turn, to pattern a target layer where a metal line will be formed.Type: GrantFiled: December 7, 2020Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jiann-Horng Lin, Cheng-Li Fan, Chih-Hao Chen
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Patent number: 11594469Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.Type: GrantFiled: April 12, 2021Date of Patent: February 28, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY. LTD.Inventors: Shih-Chang Ku, Hung-Chi Li, Tsung-Shu Lin, Tsung-Yu Chen, Wensen Hung
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Patent number: 11569454Abstract: Provided are an organic-light-emitting device and a display apparatus including the same. The organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode and including at least one light-emitting unit, wherein the at least one light-emitting unit includes: an emission layer; and a hole transport region between the first electrode and the emission layer and including a first hole transport (HT) layer, the emission layer includes a host, the first HT layer includes a first compound, a minimum bond dissociation energy (BDE1HT) of the first compound is larger than a triplet energy (T1,host) of the host, and a minimum bond dissociation energy (BDEhost) of the host is larger than the triplet energy (T1,host) of the host.Type: GrantFiled: March 9, 2020Date of Patent: January 31, 2023Assignee: Samsung Display Co., Ltd.Inventors: Jaeyong Lee, Taekyung Kim, Minkyung Kim, Seulong Kim, Pilgu Kang, Jiyoung Kwon, Soonchul Chang, Jaehoon Hwang