Patents Examined by Hung K. Vu
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Patent number: 11804427Abstract: A semiconductor package may include a redistribution substrate, a connection terminal, and a semiconductor chip sequentially stacked. The redistribution substrate may include an insulating layer, a plurality of redistribution patterns, which are vertically stacked in the insulating layer, and each of which includes interconnection and via portions, and a bonding pad on the interconnection portion of the topmost redistribution pattern. The topmost redistribution pattern and the bonding pad may include different metallic materials. The bonding pad may have first and second surfaces opposite to each other. The first surface of the bonding pad may be in contact with a top surface of the interconnection portion of the topmost redistribution pattern. A portion of the second surface of the bonding pad may be in contact with the connection terminal. The insulating layer may be extended to be in contact with the remaining portion of the second surface.Type: GrantFiled: February 17, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dongkyu Kim, Seokhyun Lee, Kyoung Lim Suk, Jaegwon Jang, Gwangjae Jeon
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Patent number: 11804483Abstract: A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.Type: GrantFiled: February 17, 2021Date of Patent: October 31, 2023Inventors: Gyu-Hwan Ahn, Sung-Soo Kim, Chae-Ho Na, Dong-Hyun Roh, Sang-Jin Hyun
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Patent number: 11798907Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.Type: GrantFiled: November 6, 2020Date of Patent: October 24, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Sheng Lin, Yun-Ching Hung, An-Hsuan Hsu, Chung-Hung Lai
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Patent number: 11784112Abstract: An integrated circuit package is formed by positioning an integrated circuit die on a die pad of a leadframe; connecting a bond wire between the die and a bond pad of the leadframe; encapsulating the bond wire, die, and bond pad with an encapsulant material to form a first mold cap of the integrated circuit package; after the encapsulating, bending one or more leads of the leadframe to form one or more bent leads; and encapsulating the first mold cap and a portion of a bend of the one or more bent leads with the encapsulant material to form a second mold cap.Type: GrantFiled: August 30, 2021Date of Patent: October 10, 2023Assignee: NXP USA, Inc.Inventors: Jian Song, Jun Li, Xingshou Pang, Mingchuan Han, Jinzhong Yao, Xuesong Xu
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Patent number: 11784215Abstract: This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.Type: GrantFiled: March 2, 2020Date of Patent: October 10, 2023Assignee: Google LLCInventors: Nam Hoon Kim, Teckgyu Kang, Scott Lee Kirkman, Woon-Seong Kwon
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Patent number: 11784137Abstract: A semiconductor device in which reliability and production yield are improved by reducing or preventing the spreading of cracks that may occur in the die sawing process, and a method for fabricating the same are provided. The semiconductor device includes a substrate which includes a first chip region and a scribe lane region surrounding the first chip region, a first low-k insulating film, which includes a first insulating material having a dielectric constant lower than silicon oxide, on the substrate in the first chip region, a wiring structure, which includes a second low-k insulating film including the first insulating material and a first wiring pattern in the second low-k insulating film, on the substrate in the scribe lane region, and a first protective insulating film, which includes a second insulating material different from the first insulating material, between the first low-k insulating film and the wiring structure.Type: GrantFiled: January 19, 2021Date of Patent: October 10, 2023Inventors: Yun Rae Cho, Ae Nee Jang, Seung Hun Han
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Patent number: 11784160Abstract: An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.Type: GrantFiled: September 23, 2020Date of Patent: October 10, 2023Assignee: International Business Machines CorporationInventors: Katsuyuki Sakuma, Krishna R. Tunga, Shidong Li, Griselda Bonilla
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Patent number: 11764539Abstract: A transmitting device, containing an emitting device (1) and a scanning mirror (2), which is deflectable about its center (MP) and is arranged in a housing (3) with a transparent cover element (4). The cover element (4) is formed, at least in a coupling-out region (4.2), by a section of a monocentric hemispherical shell (HK) with a center of curvature (K) and is arranged to cover the scanning mirror (2) in such a way that the center of curvature (K) of the hemispherical shell (HK) and the center (MP) of the scanning mirror (2) coincide.Type: GrantFiled: August 2, 2018Date of Patent: September 19, 2023Assignee: JENOPTIK OPTICAL SYSTEMS GMBHInventors: Uwe Schaller, Christian Raabe
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Patent number: 11764076Abstract: Certain aspects of the present disclosure generally relate to an embedded trace substrate with partially buried traces, methods for fabrication thereof, and apparatus comprising such an embedded trace substrate. One example method of fabricating an embedded trace substrate generally includes creating a pattern of conductive traces above a dielectric layer and mechanically pressing on the pattern of conductive traces such that lower portions of the conductive traces are buried in the dielectric layer.Type: GrantFiled: November 30, 2020Date of Patent: September 19, 2023Assignee: QUALCOMM INCORPORATEDInventors: Kuiwon Kang, Joan Rey Villarba Buot, Terence Cheung
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Patent number: 11764185Abstract: A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.Type: GrantFiled: August 31, 2021Date of Patent: September 19, 2023Assignee: Infineon Technologies Austria AGInventors: Kirill Trunov, Thomas Hendrix
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Patent number: 11756894Abstract: Radio-frequency (RF) integrated circuit (IC) (RFIC) packages employing a substrate sidewall partial shield for electro-magnetic interference (EMI) shielding. A RFIC package includes an IC die layer that includes a RFIC die(s) mounted on a substrate that includes substrate metallization layers, a substrate core, and substrate antenna layers. The RFIC package includes an EMI shield surrounding the IC die layer and extending down shared sidewalls of the IC die layer and the substrate. The EMI shield extends down the sidewalls of the IC die layer and substrate metallization layers of the substrate to at least the interface between the substrate metallization layers and the substrate core, and without extending adjacent to the sidewall of the substrate antenna layers. In this manner, antenna performance of the antenna module may not be degraded, because extending the EMI shield down sidewalls of the substrate antenna layers can create a resonance cavity in the substrate.Type: GrantFiled: May 20, 2020Date of Patent: September 12, 2023Assignee: QUALCOMM INCORPORATEDInventors: Jeahyeong Han, Rajneesh Kumar, Jeongil Jay Kim, Chin-Kwan Kim
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Patent number: 11735664Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: GrantFiled: August 30, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Patent number: 11735510Abstract: A printed circuit board includes an insulating layer; and an external connection pad embedded in the insulating layer and having one surface exposed. The external connection pad may include a base pad portion having a first pattern portion in contact with a side surface of the insulating layer and having a first width, and a second pattern portion protruding from the first pattern portion and having a second width smaller than the first width, the second pattern portion having a gap with the side surface of the insulating layer, and a surface treatment layer disposed in the gap between the second pattern portion and the insulating layer and extending on an upper surface of the second pattern portion.Type: GrantFiled: April 12, 2021Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventor: Chan Hoon Ko
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Patent number: 11728314Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
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Product-sum operation device, neuromorphic device, and method for using product-sum operation device
Patent number: 11726745Abstract: A product-sum operation device, a neuromorphic device, and a method for using the product-sum operation device are provided which can, when applied to a neural network, curb the possibility that the performance of the neural network may be greatly impaired. The product-sum operation device includes a product operator and a sum operator. The product operator includes a plurality of product operation elements, each of which is a resistance change element. The sum operator includes an output detector that detects the sum of outputs from the plurality of product operation elements and the resistance change element includes a fuse portion which is disconnected when a malfunction which increases an output current from the resistance change element has occurred in the resistance change element.Type: GrantFiled: December 12, 2018Date of Patent: August 15, 2023Assignee: TDK CORPORATIONInventor: Tatsuo Shibata -
Patent number: 11728366Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an image sensor disposed within a substrate. The substrate has sidewalls and a horizontally extending surface defining one or more trenches extending from a first surface of the substrate to within the substrate. One or more isolation structures are arranged within the one or more trenches. A doped region is arranged within the substrate laterally between sidewalls of the one or more isolation structures and the image sensor and vertically between the image sensor and the first surface of the substrate. The doped region has a higher concentration of a first dopant type than an abutting part of the substrate that extends along opposing sides of the image sensor.Type: GrantFiled: November 5, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
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Patent number: 11710735Abstract: On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.Type: GrantFiled: January 6, 2021Date of Patent: July 25, 2023Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Kenji Sasaki, Yasuhisa Yamamoto
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Patent number: 11710711Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.Type: GrantFiled: June 18, 2021Date of Patent: July 25, 2023Assignee: STMicroelectronics (Rousset) SASInventors: Abderrezak Marzaki, Mathieu Lisart
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Patent number: 11705413Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.Type: GrantFiled: December 14, 2021Date of Patent: July 18, 2023Assignee: MEDIATEK INC.Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
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Patent number: 11694964Abstract: A flexible circuit board according to an embodiment of the present invention comprises: a substrate; a first wiring pattern layer disposed on a first surface of the substrate; a second wiring pattern layer disposed on a second surface opposite the first surface of the substrate; a first dummy pattern part disposed on the second surface of the substrate on which the second wiring pattern layer is not disposed; a first protection layer disposed on the first wiring pattern layer; and a second protection layer disposed on the second wiring pattern layer and the first dummy pattern part, wherein at least a part of the first dummy pattern part overlaps with the first wiring pattern layer in a vertical direction.Type: GrantFiled: December 22, 2021Date of Patent: July 4, 2023Assignee: LG INNOTEK CO., LTD.Inventors: Jun Young Lim, Hyung Kyu Yoon, Sung Min Chae