Abstract: A semiconductor device includes a semiconductor substrate, a transistor region, a diode region, a boundary trench gate, and a carrier control region. The boundary trench gate is provided in a boundary portion between the transistor region and the diode region. The carrier control region is provided as a surface layer of the semiconductor substrate at a position closer to the boundary trench gate than the source layer located between the boundary trench gate and the trench gate. A concentration of first conductivity type impurities contained in the carrier control region is higher than a concentration of the first conductivity type impurities contained in the source layer or a concentration of second conductivity type impurities contained in the carrier control region is lower than a concentration of the second conductivity type impurities contained in the source layer.

Abstract: The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.

Abstract: To improve an on-resistance of a semiconductor device. A plurality of collector regions are formed at a predetermined interval on a bottom surface of a drift layer made of SiC. Next, on the bottom surface of the drift layer, both of the drift layer and a collector region via a silicide layer are connected to a collector electrode.

Abstract: According to one embodiment, a semiconductor device includes first and second electrodes, first to third semiconductor regions, a structure body, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided selectively on the second semiconductor region. The structure body includes an insulating part and a conductive part. The insulating part is arranged with the third and second semiconductor regions, and a portion of the first semiconductor region. The conductive part is provided in the insulating part. The conductive part includes a portion facing the first semiconductor region. The gate electrode faces the second semiconductor region. The second electrode is provided on the second and third semiconductor regions, and the structure body. The second electrode is electrically connected to the second and third semiconductor regions, and the conductive part.

Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first portion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.

Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

Abstract: A semiconductor package includes a photonic die, an encapsulated electronic die, a substrate, and a lens structure. The photonic die includes an optical coupler. The encapsulated electronic die is disposed over and bonded to the photonic die. The encapsulated electronic die includes an electronic die and an encapsulating material at least laterally encapsulating the electronic die. The substrate is disposed over and bonded to the encapsulated electronic die. The lens structure is disposed over the photonic die and is overlapped with the optical coupler from a top view. The optical coupler is configured to be optically coupled to an optical signal source through the lens structure.

Abstract: A semiconductor device includes a region of semiconductor material comprising a major surface and a first conductivity type and a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench; an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench; and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. An interlayer dielectric (ILD) structure is over the major surface. A conductive region is within the active trench and extends through the ILD structure, the gate electrode, and the IPD, and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode by a dielectric spacer. The gate electrode comprises a shape that surrounds the conductive region in a top view so that the gate electrode is uninterrupted by the conductive region and the dielectric spacer.

Abstract: A semiconductor device having IGBT, FWD and separate cell regions in a common semiconductor substrate, includes: a drift layer; a base layer; trench gate structures; an emitter region; a collector layer; a cathode layer; a first electrode; and a second electrode. The IGBT region having a first gate electrode in first and second IGBT trenches with a grid pattern is on the collector layer, and the FWD region with a second gate electrode in first and second FWD trenches with a grid pattern is on the cathode layer.

Abstract: A phase change memory and a method of fabricating the same are provided. The phase change memory includes a lower electrode, an annular heater disposed over the lower electrode, an annular phase change layer disposed over the annular heater, and an upper electrode. The annular phase change layer and the annular heater are misaligned in a normal direction of the lower electrode. The upper electrode is disposed over the annular phase change layer, in which the upper electrode is in contact with an upper surface of the annular phase change layer. The present disclosure simplifies the manufacturing process of the phase change memory, reduces the manufacturing cost, and improves the manufacturing yield. In addition, a contact surface between the heater and the phase change layer of the phase change memory of the present disclosure is very small, so that the phase change memory has an extremely low reset current.

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on?VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi ?Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

Abstract: An RC IGBT includes, in an active region, an IGBT section and at least three diode sections. The arrangement of the diode sections obeys a design rule.

Abstract: Provided is a semiconductor device having improved breakdown resistance during recovery operation. A semiconductor device according to the present application is a semiconductor device in which an insulated gate bipolar transistor region and a diode region are provided adjacent to each other. The insulated gate bipolar transistor region includes an emitter layer having a short-side direction in a first direction in a plan view. The diode region includes carrier injection suppression layer having a short-side direction in a second direction in a plan view. In a plan view, a width of the carrier injection suppression layer in the second direction is smaller than a width of the emitter layer in the first direction.

Abstract: A semiconductor device includes an IGBT region and a diode region provided to be adjacent to each other in a semiconductor substrate further includes: a boundary trench having, in a position in which the IGBT region and the diode region are adjacent to each other in plan view, a bottom surface positioned in a drift layer to be deeper than an active trench or a dummy trench, and one side wall and another side wall that face each other; and a boundary trench gate electrode, which faces a base layer, an anode layer, and the drift layer via a boundary trench insulating film and is provided from the one side wall to the other side wall of the boundary trench across a region that faces the drift layer in the boundary trench.

Abstract: A lighting device is specified. The lighting device comprises a phosphor having the general molecular formula (MA)a(MB)b(MC)c(MD)d(TA)e(TB)f(TC)g(TD)h(TE)i(TF)j(XA)k(XB)l(XC)m(XD)n:E. In this case, MA is selected from a group of monovalent metals, MB is selected from a group of divalent metals, MC is selected from a group of trivalent metals, MD is selected from a group of tetravalent metals, TA is selected from a group of monovalent metals, TB is selected from a group of divalent metals, TC is selected from a group of trivalent metals, TD is selected from a group of tetravalent metals, TE is selected from a group of pentavalent elements, TF is selected from a group of hexavalent elements, XA is selected from a group of elements which comprises halogens, XB is selected from a group of elements which comprises O, S and combinations thereof, XC=N and XD=C and E=Eu, Ce, Yb and/or Mn. The following furthermore hold true: a+b+c+d=t; e+f+g+h+i+j=u; k+l+m+n=v; a+2b+3c+4d+e+2f+3g+4h+5i+6j?k?2l?3m?4n=w; 0.8?t?1; ?3.

Abstract: A light emitting device package including a printed circuit board having a front surface and a rear surface, at least one light emitting device disposed on the front surface and emitting light in a direction toward the front surface, and a molding layer disposed on the printed circuit board and surrounding the light emitting device, in which the light emitting device includes a light emitting structure disposed on the printed circuit board, a substrate disposed on the light emitting structure, and a plurality of bump electrodes disposed between the light emitting structure and the printed circuit board, and the molding layer covers an upper surface of the substrate and includes a fine concavo-convex part formed on a surface of the molding layer exposed to the outside.

Abstract: A main semiconductor device element is a vertical MOSFET with a trench gate structure, containing silicon carbide as a semiconductor material, and having first and second p+-type regions that mitigate electric field applied to bottoms of trenches. The first p+-type regions are provided separate from the p-type base regions and face the bottoms of the trenches in a depth direction. The first p+-type regions are disposed at an interval that is at most 1.0 ?m, in a first direction that is a direction in which gate electrodes extend. The second p+-type regions are provided between adjacent trenches of the trenches, separate from the first p+-type regions and the trenches, and in contact with the p-type base regions. In the first direction that is the direction in which the trenches, the second p+-type regions extend in a linear shape having a length that is substantially equal to that of the trenches.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, first and third semiconductor regions of a first conductivity type, second and fourth semiconductor regions of a second conductivity type, a gate electrode and a second electrode. The third semiconductor region is disposed on one portion of the second semiconductor region. The fourth semiconductor region is disposed on another portion of the second semiconductor region, is positioned below the third semiconductor region. The second electrode includes first and second portions separated from each other and allowing the fourth semiconductor region to be positioned therebetween, and the third portion disposed on the first and second portions and arranged with the third semiconductor region. The first, second, and third portions are in contact with the fourth semiconductor region.

Abstract: A semiconductor device, including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at a surface thereof, a plurality of gate insulating films in contact with the second semiconductor layer, a plurality of gate electrodes respectively provided on the gate insulating films, a plurality of first electrodes provided on the second semiconductor layer and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a capping layer that is a conductive metal nitride such as MoN contacts an opposite surface of the Hk enhancing layer with respect to the first interface to reduce interdiffusion of oxygen and nitrogen compared with a TiN capping layer and maintain an acceptable resistance x area (RA) product. In other embodiments, the capping layer may comprise an insulating nitride such as AlN that is alloyed with a conductive metal to minimize RA. Furthermore, a metallic buffer layer may be inserted between the capping layer and Hk enhancing layer. As a result, electrical shorts are reduced and the magnetoresistive ratio is increased.