Abstract: A data storage blade includes a plurality of data storage cartridges, with each of the plurality of data storage cartridges comprising at least one data storage medium. The data storage blade also includes shared drive electronics (SDE) external to the plurality of data storage cartridges. The SDE is configured to control data access operations on different data storage cartridges of the plurality of data storage cartridges. The data storage blade further includes a controller-override mechanism activatable to disable communication between the SDE and the plurality of data storage cartridges.

Abstract: A distributed data storage system can be configured with a host connected to a first device and an initialization module that performs a default initialization procedure on the first device in response to detecting the first device has an unknown manufacturing origin. Conducting the default initialization procedure may allow the first device to service data access requests from the host. In response to the connection of a second device to the host and initialization module, a manufacturing origin of the second device is identified with the initialization module before the initialization module customizes the default initialization procedure to a custom procedure that is executed to allow the second device to satisfy a background operation prescribed by the initialization module.

Abstract: A PCIe controller and a loopback path using the PCIe controller. The PCIe controller includes: a transport layer transmission module, a transport layer reception module, a memory access module, and a memory, wherein the transport layer transmission module includes a first loopback control module, the transport layer reception module includes a second loopback control module, and the first loopback control module is coupled to the second loopback control module; the memory access module is coupled to the transport layer transmission module and the transport layer reception module, and the memory access module is also coupled to the memory.

Abstract: A flash drive includes a main housing, a USB adapter unit mounted in the main housing and extending out of the main housing, an inner housing movably connected to the main housing, and a flash memory unit including a flash memory that is mounted in the inner housing, and a USB-A plug that is connected to the flash memory. The inner housing is operable to move, with respect to the main housing, between a USB-C position, where the USB-A plug is electrically connected to the USB adapter unit to allow for data transfer therebetween, and a USB-A position, where the USB-A plug is detached from the USB adapter unit to prevent data transfer therebetween, such that data is transferable to and from the flash memory via the USB-A plug.

Abstract: A snapshot is taken of at least a portion of a file system having a set of files to retain over a retention duration. The snapshot is taken at a level of the file system or a directory of the file system. A retention lock is applied to the snapshot to block, over the retention duration, operations involving deletion of the snapshot. The retention lock is not applied to the set of files.

Abstract: Techniques are provided for caching of machine learning model training parameters. One method comprises training a machine learning model using a given training dataset; and caching a parameter of the machine learning model from the training with the given training dataset. The cached parameter of the machine learning model is used for a subsequent training of the machine learning model. The caching may be performed after each of multiple iterations of the training of the machine learning model. A given cached iteration of the training of the machine learning model may be identified using a key based on: (i) a hash of the given training dataset, (ii) a hash of the machine learning model parameter, and/or (iii) hyperparameters of the machine learning model. The caching of a given iteration of the machine learning model may occur when the given cached iteration is not found in a cache memory.

Abstract: A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

Abstract: An apparatus comprises a processing device configured to identify storage workloads to be run on a storage system, and to determine a mix of input/output (TO) patterns associated with the identified storage workloads, the mix of IO patterns comprising a first set of IO patterns characterizing types of IO operations performed by a first storage workload and at least a second set of IO patterns characterizing types of IO operations performed by a second storage workload. The processing device is also configured to calculate an affinity metric for the mix of IO patterns, the calculated affinity metric characterizing a difference between (i) performance metrics for the mix of IO patterns running concurrently and (ii) the first and second sets of IO patterns running individually. The processing device is further configured to allocate the identified storage workloads to storage devices of the storage system based on the calculated affinity metric.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.

Abstract: A multi-stream solid-state device (SSD) includes a normal-access memory associated with a first stream ID, a high-access memory having a higher endurance than the normal-access memory and being associated with a second stream ID, a controller processor, and a processor memory coupled to the controller processor, wherein the processor memory has stored thereon instructions that, when executed by the controller processor, cause the controller processor to perform identifying a data stream ID of an input data stream as one of the first and second stream IDs, in response to identifying the data stream ID as the first stream ID, storing the input data stream in the normal-access memory, and in response to identifying the data stream ID as the second stream ID, storing the input data stream in the high-access memory.

Abstract: Systems and methods are described for smoothing-out latency of IO operations processed by a distributed storage system. In some examples, latency is distributed among IO operations to more evenly spread processing of the IO operations over an IO processing interval. A target latency for IO operations for a volume of a distributed storage system is periodically calculated each sample period based on the number of IO operations to be processed during the next IO processing interval for the volume. As IO operations are received for the volume, a latency may be associated with the IO operation based on the target latency and the IO operation may be queued or synchronously processed as appropriate. Responsive to expiration of a time period that is based on at time at which a given IO operation at the head of the queue was received and the assigned latency, the given IO operation is dequeued and processed.

Abstract: Aspects of the disclosure are directed to a storage device including a memory and a controller. The memory may include a plurality of flash memory blocks such as single level cell (SLC) blocks and multi-level cell (MLC) blocks. The controller may maintain a read count of each of the SLC blocks to determine which of the blocks contains data associated with the highest number of read commands. Based on the read commands, the controller may relocate the associated data into pages of MLC blocks that have a lower number of senses required to read the data stored in those blocks.

Abstract: A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.

Abstract: A network interface controller (NIC) capable of on-demand paging is provided. The NIC can be equipped with a host interface, an operation logic block, and an address logic block. The host interface can couple the NIC to a host device. The operation logic block can obtain from a remote device, a request for an operation based on a virtual memory address. The address logic block can obtain, from the operation logic block, a request for an address translation for the virtual memory address and issue an address translation request to the host device via the host interface. If the address translation is unsuccessful, the address logic block can send a page request to a processor of the host device via the host interface. The address logic block can then determine that a page has been allocated in response to the page request and reissue the address translation request.

Abstract: Matrix multiplication process is segregated between two separate dies—a memory die and a compute die to achieve low latency and high bandwidth artificial intelligence (AI) processor. The blocked matrix-multiplication scheme maps computations across multiple processor elements (PE) or matrix-multiplication units. The AI architecture for inference and training includes one or more PEs, where each PE includes memory (e.g., ferroelectric (FE) memory, FE-RAM, SRAM, DRAM, MRAM, etc.) to store weights and input/output I/O data. Each PE also includes a ring or mesh interconnect network to couple the PEs for fast access of information.

Abstract: A first correspondence table indicates a correspondence relation between logical blocks of a first file and physical blocks of a physical storage. A second correspondence table indicates a correspondence relation between logical blocks of a second file and the logical blocks of the first file. An access request receiving section receives an access request for the second file. A block conversion section refers to the second correspondence table, identifies a logical block of the first file associated with the logical block of the second file that is subject to the access request, and then refers to the first correspondence table to identify a physical block of the physical storage associated with the identified logical block of the first file. An accessing section accesses the identified physical block.

Abstract: The invention is to efficiently exchange storage programs. A storage program in an active state and a storage program in a standby state in a storage program group each change metadata thereof when the storage program in the active state writes data. When update of the storage programs including arranging post-update storage programs in storage nodes and generating new-version metadata based on old-version metadata by the post-update storage programs is to be performed, the post-update storage program in the standby state generates the new-version metadata based on the old-version metadata is performed for the storage programs in the plurality of storage nodes while replacing the active state and the standby state of the storage programs with each other in the plurality of storage programs in the storage program group.

Abstract: Disclosed are various examples of providing efficient bit compression for direct mapping of physical memory addresses. In some examples, a hypervisor operating system component generates a mask of used address space bits indicated by memory map entries for a computing device. A longest range of unused address space bits is identified using the mask. The memory map entries are transformed to omit the longest range of unused address space bits.

Abstract: Disclosed herein is a system for improving the user experience in the face of a regression by returning resources that offer a service to a “last known good” upgrade. In other words, the state of the resources is reconfigured to scale back from recent upgrade(s), the deployments of which likely caused the regression, to a previous upgrade that is known to have little or no effect on the user experience. To identify a problem, the system collects performance data from different resource units that make up a cloud-based platform. The performance data is collected for each upgrade event in a sequence of upgrade events that are currently deployed or being deployed. The system continually tracks and analyzes qualification data collected for each of the deployed upgrade events. The system can tag an upgrade event as the last known good upgrade event when the collected qualification data satisfies predefined qualifications.

Abstract: A cache of a processor includes a cache controller to implement a cache management policy for the insertion and replacement of cache lines of the cache. The cache management policy assigns replacement priority levels to each cache line of at least a subset of cache lines in a region of the cache based on a comparison of a number of accesses to a cache set having a way that stores a cache line since the cache line was last accessed to a reuse distance determined for the region of the cache, wherein the reuse distance represents an average number of accesses to a given cache set of the region between accesses to any given cache line of the cache set.