Patents Examined by Ilwoo Park
  • Patent number: 11461227
    Abstract: A storage device for performing a garbage collection operation using a partial block erase operation includes: a memory device including a plurality of main blocks each including a plurality of sub-blocks; and a memory controller configured to perform a garbage collection operation for securing free blocks in which no data is stored, among the main blocks, wherein the memory controller includes a write handler configured to erase at least a portion of a target block, among the main blocks, according to whether an amount of valid data in at least one victim block exceeds a storage capacity of one main block.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventor: Byoung Sung You
  • Patent number: 11461015
    Abstract: A technique is configured to provide various data protection schemes, such as replication and erasure coding, for data blocks of volumes served by storage nodes of a cluster configured to perform deduplication of the data blocks. Additionally, the technique is configured to ensure that each deduplicated data block complies with data redundancy guarantees of the data protection schemes, while improving storage space of the storage nodes. In order to satisfy the data integrity guarantees while improving available storage space, the storage nodes perform periodic garbage collection for data blocks to optimize storage in accordance with currently applicable data protection schemes.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: October 4, 2022
    Assignee: NetApp, Inc.
    Inventors: Christopher Clark Corey, Daniel David McCarthy, Sneheet Kumar Mishra, Austino Nicholas Longo
  • Patent number: 11449257
    Abstract: An apparatus comprises a host device configured to communicate over a network with a storage system. The host device establishes a migration session in the host device for migration of a source logical storage device accessible utilizing a first access protocol to a target logical storage device accessible utilizing a second access protocol, and migrates the source logical storage device to the target logical storage device utilizing a multi-path layer of the host device. The multi-path layer maintains separate device identities for the respective source and target logical storage devices in conjunction with the migration session but presents a corresponding composite device having a single device identity to one or more applications executing on the host device. The multi-path layer translates one or more commands directed to the composite device in the first access protocol to one or more commands in the second access protocol.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 20, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinay G. Rao, Sanjib Mallick, Natasha Gaurav, Arieh Don
  • Patent number: 11442629
    Abstract: A computer-implemented method to reduce Input/Output (I/O) command latency. The method includes receiving, by a first storage pool, a plurality of I/O commands, wherein the first storage pool includes a first throttling limit, and the first throttling limit. The method further includes determining a first processing rate of the first storage pool is at the first throttling limit. The method also includes determining a second processing rate of a second storage pool is below a second throttling limit, wherein the second storage pool is communicatively coupled to the first storage pool. The method includes sending, by the first storage pool to the second storage pool, one or more of the plurality of I/O commands. The method further includes processing, by the second storage pool, the one or more I/O commands of the plurality of I/O commands. The method includes returning processed I/O commands to the host.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 13, 2022
    Assignee: International Business Machines Corporation
    Inventors: Sanjay Tripathi, Kushal S. Patel, Rohan Mohan Salvi, Sarvesh S. Patel
  • Patent number: 11379396
    Abstract: A memory card access module and a memory card access method are provided. The memory card access method is applied to an electronic device. A processing unit of the electronic device accesses a memory card through a memory card slot. The method includes steps of: detecting whether the memory card supports a Peripheral Component Interconnect Express (PCIe) interface; when the memory card does not support the PCIe interface, controlling the processing unit to access the memory card through a data transmission path and performing data format conversion between a transmission interface and the PCIe interface using a memory card access unit disposed on the data transmission path; and when the memory card supports the PCIe interface, controlling the processing unit to access the memory card through a PCIe data transmission path that allows the processing unit and the memory card to transmit data through the PCIe interface.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: July 5, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Jiunn-Hung Shiau, Neng-Hsien Lin
  • Patent number: 11372547
    Abstract: Methods and systems for compression of aging data during compaction are disclosed. A method includes: ingesting a plurality of data objects into a dispersed storage network (DSN); determining that a compaction threshold is met for a storage medium in the DSN; and compacting the storage medium, the compaction including, for each of the plurality of data objects: determining a number of times the data object has been compacted; in response to the number of times the data object has been compacted exceeding a predetermined threshold, compressing the data object and rewriting the compressed data object to a new area on a storage medium; and in response to the number of times the data object has been compacted not exceeding the predetermined threshold, rewriting the data object to the new area on the storage medium without compressing the data object.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: June 28, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praveen Viraraghavan, Ethan Wozniak, Ilya Volvovski
  • Patent number: 11372792
    Abstract: A firmware enumerates the buses of root bridges in the computing system. If an OOR condition occurs during enumeration of the buses, the firmware determines the number of required buses for each root bridge causing an OOR condition. The number of required buses for bridge devices connected to each root bridge causing an OOR condition can be identified using the same set of bus numbers. Once the firmware has determined the number of buses required by each root bridge, including those not causing an OOR condition, the firmware reallocates the number of available buses between the root bridges such that each root bridge is allocated a number of the available buses greater than or equal to the number of required buses. The firmware stores data identifying the allocation and restarts the computing device. Upon rebooting, the computing system utilizes the new allocation of bus numbers to eliminate the OOR condition.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: June 28, 2022
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Naresh Kollu, Harikrishna Doppalapudi
  • Patent number: 11366590
    Abstract: A host device is configured to communicate over a network with a storage system comprising a plurality of storage devices. The host device comprises a multi-path input-output (MPIO) driver configured to control delivery of input-output (IO) operations from the host device to the storage system over selected ones of a plurality of paths through the network. The MPIO driver is further configured to determine IO processing performance for each of at least a subset of the paths, and to dynamically adjust a path selection algorithm utilized in selecting particular ones of the paths for delivery of the IO operations from the host device to the storage system based at least in part on the determined performance. For example, dynamically adjusting a path selection algorithm illustratively comprises activating a particular one of a plurality of distinct path selection algorithms available to the MPIO driver and/or adjusting one or more parameters of a given path selection algorithm.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 21, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sanjib Mallick, Vinay G. Rao, Arieh Don
  • Patent number: 11347419
    Abstract: Data convolution for geographically diverse storage is disclosed, wherein the data convolution is based on a valency metric, determination, parameter, etc. Valency can be correlated to a data object and can be inherited by a chunk comprising the data object. Valency can indicate permitted levels of convolution for a chunk. A chunk resulting from convolving at least two other contributing/participating chunks can be determined to have a valency that can be less than either of the two contributing/participating chunks. A chunk with a zero valence can be restricted from contributing to a convolution. Where the at least two other chunks both have infinite valency, the resulting convolved chunk can also have infinite valency. A chunk resulting from convolving participating chunks having mixed valency values can be reconvolved. Valency can enable orchestrating convolution of chunks, for example, to conserving storage space, mitigate computing resource consumption, etc.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: May 31, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Yohannes Altaye
  • Patent number: 11347645
    Abstract: Managing a cache memory in a storage system includes maintaining a queue that stores data indictive of the read requests for a particular logical storage unit of the storage system in an order that the read requests are received by the storage system, receiving a read request for a particular page of the particular logical storage unit, and removing a number of elements in the queue and resizing the queue in response to the queue being full. Managing the cache memory also includes placing data indicative of the read request in the queue, determining a prefetch metric that varies according to a number of adjacent elements in a sorted version of the queue having a difference that is less than a predetermined value and greater than zero, and prefetching a plurality of pages that come after the particular page sequentially if the prefetch metric is greater than a predefined value.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Vinicius Gottin, Jonas F. Dias, Hugo de Oliveira Barbalho, Romulo D. Pinho, Tiago Calmon
  • Patent number: 11347675
    Abstract: A system includes a first embedded controller to manage a management interface of a mobile device. A second embedded controller manages a display panel at the system. The first embedded controller receives a first event notification of an insertion of a sled in the system, and determines a pending storage mapping associated with the sled. The first embedded controller displays, at the management interface, information associated with the pending storage mapping associated with the sled. The second embedded controller generates a graphical user interface with information associated with the pending storage mapping associated with the sled. The graphical user interface is updated in response to user input.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: May 31, 2022
    Assignee: Dell Products L.P.
    Inventors: Christopher Abella Poblete, Santosh Kumar Bidaralli
  • Patent number: 11327675
    Abstract: Examples of a data migration system are provided. The system may receive a data migration requirement. The system may sort the data stored in the on-premise data warehouse into a plurality of data domains. The system may map the plurality of data domains to a usage parameter index and a storage parameter index to determine a data usage pattern and a data storage pattern. The system may evaluate the data storage pattern and the data usage pattern to determine a data assessment index. The system may determine a data migration index from mapping a plurality of cloud platforms to the data assessment index. The system may determine a data migration model compatible with the data assessment index. The system may generate a data migration output comprising the layout for transferring data stored in the on-premise data warehouse to a compatible cloud platform to resolve the data migration requirement.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 10, 2022
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Jayant Swamy, Aniruddha Ray, Anshul Pandey, Ritesh Padmanabhan Iyer, Rahul Das, Manish Shandhil
  • Patent number: 11301140
    Abstract: A storage server includes an interface to a storage over fabric network, a plurality of input/output (I/O) queues (IOQs), a plurality of non-volatile data storage devices to store data received from a host computer system over the interface to the storage over fabric network, and a processor to set a maximum number of the IOQs to be provisioned for the host computer system and a maximum depth of the IOQs to be provisioned for the host computer system.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Phil C. Cayton, Rajalaxmi Angadi, David B. Minturn
  • Patent number: 11281585
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Patent number: 11281589
    Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that requests return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Harold Robert George Trout
  • Patent number: 11283646
    Abstract: The present disclosure relates to a method of monitoring Local Interconnect Network (LIN) nodes and a monitoring device performing the method. In an aspect a method of a monitoring device of monitoring a plurality of LIN buses is provided, wherein at least one LIN node is connected to each LIN bus, said plurality of LIN buses being interconnected via the monitoring device. The method comprises detecting, for each LIN bus, any dominant data being sent over said each LIN bus by a LIN node connected to said each LIN bus and routing said any dominant data received by the monitoring device over said each LIN bus to all remaining LIN buses without overwriting any dominant data sent over the remaining LIN buses.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: March 22, 2022
    Assignee: Volvo Car Corporation
    Inventor: Anders Antonsson
  • Patent number: 11275509
    Abstract: A computer system comprising: a data storage medium comprising a plurality of storage devices configured to store data; and a data storage controller coupled to the data storage medium; wherein the data storage controller is configured to: receive read and write requests targeted to the data storage medium; schedule said read and write requests for processing by said plurality of storage devices; detect a given device of the plurality of devices is exhibiting an unscheduled behavior comprising variable performance by one or more of the plurality of storage devices, wherein the variable performance comprises at least one of a relatively high response latency or relatively low throughput; and schedule one or more reactive operations in response to detecting the occurrence of the unscheduled behavior, said one or more reactive operations being configured to cause the given device to enter a known state.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: March 15, 2022
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Craig Harmer, John Hayes, Bo Hong, Ethan Miller, Feng Wang
  • Patent number: 11256633
    Abstract: A processing system includes at least one core, a plurality of accelerator function unit (AFU) and a memory access unit. The memory access unit includes at least one pipeline resource and an arbitrator. The core develops a plurality of tasks. Each of the AFU is used to execute at least one of the tasks which corresponds to several memory access requests. The arbitrator selects one of the AFUs using a round-robin method at each clock period to transmit a corresponding memory access request of the selected AFU to the pipeline resource, so that the selected AFU executes the memory access request through the pipeline resource to read or write data related to the task.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: February 22, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Xiaoyang Li, Chen Chen, Zongpu Qi, Tao Li, Xuehua Han, Wei Zhao, Dongxue Gao
  • Patent number: 11249930
    Abstract: A network input/output structure of an electronic device includes a FPGA module, a multiple of UART voltage conversion transceivers, at least one network connector and at least one detection module. Each UART voltage conversion transceiver has an input/output pin definition of a brand specification of a network device. The FPGA module uses the detection module to detect the pin definition of an external network device to confirm the brand specification of the network device and turn on a voltage conversion chip of the UART voltage conversion transceiver of the brand specification, so that the external network device can transmit network information with the electronic device automatically.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 15, 2022
    Assignee: PORTWELL INC.
    Inventor: Yen-Lung Chou
  • Patent number: 11243695
    Abstract: A method, system, and computer program product for implementing indexes in a dispersed storage network (dsNet) are provided. The method accesses an unordered work queue containing a set of key-value pairs. A subset of expired key-value pairs are determined from the set of key-value pairs. The method transmits a work request to a plurality of data source units. The work request indicates a key-value pair being selected at random from the subset of expired key-value pairs. A threshold number of work responses is received from the plurality of data source units. The work responses include a set of available key-value pairs. The method selects an available key-value pair from the set of available key-value pairs and generates a work lease on the available key-value pair.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: February 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Thomas Dubucq, Gregory R. Dhuse