Abstract: The invention provides a data storage device capable of self-accessing data file, which comprises a data storage unit and a microprocessor. The data storage unit includes a controller and a plurality of flash memories. The microprocessor is provided with an operating system, and is connected to the data storage unit through a data transmission interface. The operating system is configured with a file system, and a driver program of the data transmission interface. The operating system of the microprocessor performs a data access operation to the data storage unit via the driver program to obtain a raw data. Then, the file system in the operating system performs a file parsing process to the raw data to parse out a file information of the raw data. Accordingly, the data storage device is capable of self-accessing the data file of the flash memories by the operating system configured in the microprocessor.

Abstract: The present disclosure generally relates to a method and device for detecting patterns in host command pointers. When a new command is received by a storage device from a host computer, host command pointers sent to the storage device are analyzed to detect any patterns within the host command pointers. If a pattern is detected, the storage device can store the host command pointers in a reduced pointer storage structure. Thereafter, the storage device can perform the command indicated by the host command pointers using the reduced pointer storage structure.

Abstract: A data processing apparatus is provided, which includes a cache to store operations produced by decoding instructions fetched from memory. The cache is indexed by virtual addresses of the instructions in the memory. Receiving circuitry receives an incoming invalidation request that references a physical address in the memory. Invalidation circuitry invalidates entries in the cache where the virtual address corresponds with the physical address. Coherency is thereby achieved when using a cache that is indexed using virtual addresses.

Abstract: A method of configuring a Universal Serial Bus (USB) connection between a first and second devices, the USB connection comprising a plurality of data channels, each having a pair of signal links, each signal link including a port at either end of the connection, and a signal wire formed of one or more physical wires extending between corresponding ports. Each of the signal links are configured with a first direction for transmission of data. The first direction is determined based on an initial required data transmission capacity in each direction between the first and second devices. Thereafter, depending on required capacity in the different directions, a selection is made which of the signal links should change their direction of transmission from the first direction to a second direction and a redirection signal is sent to each of the selected signal links to cause the change in direction of transmission.

Abstract: Embodiments are provided herein for efficient component communication and resource optimization in a disaggregated computing system. A general purpose link is provided between a plurality of devices in the disaggregated computing system. The general purpose link is used to connect the plurality of devices which respectively comprise different types of devices. A first data object is stored within one of the plurality of devices according to a past use or an expected use of the data object by at least a respective one of a set of processors within the disaggregated computing system, and the general purpose link is dynamically rewired according to a location of the first data object and a location of the at least one of the respective set of processors.

Abstract: Apparatuses and methods for providing and interpreting command packets for direct control of memory channels are disclosed herein. An example apparatus includes flash memories configured into channels and a controller coupled to the flash memories. The controller receives packets and interpret the packets based at least on a first protocol, and determines whether any packets are linked based on a link identifier included in a block of each packet. The controller arranges the subset of packets based on an index included in the block of each packet of the subset of packets, and the subset of packets are arranged in order based on the respective indexes. A target flash memory and a target channel are determined by the controller based on flash memory and channel identifiers included in the block of each of the packet of the subset of packets.

Abstract: Embodiments are provided herein for efficient component communication and resource optimization in a disaggregated computing system. A general purpose link is provided to connect a computing element to a plurality of other computing elements of the disaggregated computing system. The general purpose link is dynamically switched between a plurality of different hardware protocols to communicate with the other computing elements, where respective ones of the other computing elements comprise different types of hardware elements.

Abstract: A pipelined-data-transform-enabled data mover system includes a data mover device coupled to a memory system. The data mover device reads initial data from memory location(s) included in the memory system, and include at least one first data mover element that performs at least one intermediate data transform operation on the initial data in order to produce intermediate data. The data mover device also includes at least one second data mover element that subsequently performs at least one final data transform operation on the intermediate data in order to produce final data. The data mover device then writes the final data to memory location(s) included in the memory system. The data mover device may be configured by a processing system via a single descriptor that configures the data mover device to perform multiple read operations from different memory locations in the memory system in order to read the initial data.

Abstract: A machine learning system for configuring input devices connected to a computer cluster is provided. A computing device analyzes one or more input devices connected to one or more computer device executing within a workstation. A computer device receives one or more signals from the one or more input devices connected to the one or more computer devices executing within the workstation. A computing device converts the one or more signals from the one or more input devices connected to the one or more computer devices executing within the workstation into one or more device data. A computing device analyzes the one or more device data from the one or more input devices connected to the one or more computer devices executing within the workstation. A computer device determines a detected pattern of device data, wherein a computer device generates a key-mapping command.

Abstract: In one embodiment, an apparatus includes a multi-socket motherboard, a processor connected to a first socket on the multi-socket motherboard, and an RDMA (Remote Direct Memory Access) interface module connected to a second socket on the multi-socket motherboard and in communication with the processor over a coherency interface. The RDMA interface module provides an inter-server interface between servers in an RDMA domain. A method for transferring data between servers with RDMA interface modules is also disclosed herein.

Abstract: Moving data among a plurality of non-volatile storage devices of a storage device includes accumulating credits at each of a plurality of periodic intervals for separate portions of the devices, wherein the credits correspond to a wear rating for each of the devices, reducing credits for each of the portions at each of the periodic intervals based on an amount of data written to each of the portions during each of the intervals, on the wear rating for each of the devices, and on a percent life used for the devices, and moving data from a first one of the portions having a relatively low amount of credits to a second one of the portions having a relatively high amount of credits. The devices may be solid state drives. The wear rating may be a drive writes per day rating provided by a manufacture of the solid state drive.

Abstract: A storage system includes a plurality of physical drives and a storage controller connected to the plurality of physical drives to provide one or more volumes. Two or more volume addresses, which are two or more logical addresses, belong to each of the one or more volumes. When copy target data, which is data to be copied, is copied in a volume or between volumes, the storage controller (A) determines whether a copy destination physical drive, which is a physical drive corresponding to a copy destination volume address, is identical to a copy source physical drive which is the destination physical drive corresponding to a copy source volume address, and (B) shifts a storage position of the copy target data such that the copy destination physical drive becomes a physical drive identical to the copy source physical drive if a determination result of (A) is false.

Abstract: A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a load-type instruction. Execution of the load-type instruction generates a corresponding request that specifies a target address. The processing unit further includes a read-claim state machine that, responsive to receipt of the request, protects the load target address against access by any conflicting memory access request during a protection interval following servicing of the request.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory (NVM) and a controller. The controller communicates with an external device via virtual channels (VC) defined in PCI Express Base Specification (PCIe). The external device communicates with the NVM of the memory system per NVM Express Base Specification (NVMe). The controller manages a set of priority relation information (PRI), which maps each priority of Weighted Round Robin with Urgent Priority Class Arbitration mechanism defined in NVMe, to a specific VC. Using the PRI, the controller ensures that the same VC is used throughout the command execution transactions. Quality of Service of communication between the external device and the memory system can thus be improved.

Abstract: Disclosed are techniques regarding aspects of selectively enabling or disabling interconnects between peripheral processors. The peripheral processors may be included within a compute service provider and may be accessible via virtual machines within guest domains implemented within the compute service provider. The interconnects can be enabled or disabled depending upon whether they traverse domains of the compute service provider.

Abstract: Described herein is a technique capable of capable of managing a substrate processing apparatus efficiently. According to one aspect of the technique of the present disclosure, there is provided a substrate processing apparatus including: process performing parts configured to process a substrate based on a program; a first controller configured to process the program; and a second controller configured to control the process performing parts based on data received from the first controller, wherein the first controller is further configured to determine whether or not a first controller provided in an additional substrate processing apparatus is malfunctioning based on operation data of the first controller provided in the additional substrate processing apparatus, and to perform an alternative control for the first controller provided in the additional substrate processing apparatus when it is determined that the first controller provided in the additional substrate processing apparatus is malfunctioning.

Abstract: Disclosed are systems, methods and computer readable mediums for optimized throughput of an object based storage system. The systems, methods and computer readable mediums including receiving an I/O request to the storage system, determining a busy ratio based on a number of blocks available in a local cache and a queue size, determining an I/O speed to the storage system, the I/O speed based at least in part on the busy ratio and an upload speed, wherein the I/O speed does not exceed a current speed of the storage system, and executing the I/O request to the storage system at the I/O speed.

Abstract: The disclosure relates to detecting phase slips that may occur in a multi-lane serial datalink. Phase slips may occur when a lane experiences lane skew, which may introduce a phase slip with respect to another lane. To detect phase slippage, the system may select a reference lane from among the lanes. The system may generate a pre-deskew delta value based on a difference between the FIFO filling level of the reference lane before a deskew and the FIFO filling level of a second lane before the deskew. The system may generate a post-deskew delta value based on a difference between the FIFO filling level of the reference lane after the deskew and the FIFO filling level of the second lane after the deskew. The system may use a difference between the post-deskew delta and the pre-deskew delta to detect phase slip on the second lane relative to the reference lane.

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

Abstract: One example method includes discovering an application topology, discovering relationships between microservices that are elements of the application topology, ranking the microservices, identifying one or more of the microservices as a persistency microservice, selecting one or more persistency microservices for backup, and defining a backup policy based on the microservice relationships, the microservice rankings, and the selected persistent microservices. A backup operation is then performed that includes backing up persistent data and/or persistent metadata generated and/or modified by one or more of the persistency microservices.