Abstract: A display apparatus that displays an image includes a connection unit that is connected to an external apparatus and receives an image signal and a control signal from the external apparatus, a display unit that displays an image based on the image signal received by the connection unit, and a control unit that performs reconnection action of causing the connection unit to enter a first state in which the control unit recognizes that the external apparatus has not been connected to the connection unit and then causing the connection unit to enter a second state in which the control unit recognizes that the external apparatus has been connected to the connection unit.

Abstract: A processing device includes: a plurality of processing units that perform processes in accordance with data items read from a memory; a bus that connects the memory to the plurality of processing units; and a traffic monitor that monitors traffic on the bus with respect to the plurality of processing units, and when the traffic for one of the processing units that has been assigned access rights to the memory exceeds or reaches a prescribed upper limit, outputs a signal to the one of the processing units so as to reduce or suspend the traffic for the one of the processing units.

Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

Abstract: The disclosure relates to accessing memory content with a high temporal locality of reference. An embodiment of the disclosure stores the content in a data buffer, determines that the content of the data buffer has a high temporal locality of reference, and accesses the data buffer for each operation targeting the content instead of a cache storing the content.

Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

Abstract: The invention relates to a bus participant device (30) for receiving and transmitting data telegrams (18) via a serial data bus (12) according to a master/slave method, wherein the bus participant device (30) is configured to function, in a slave mode, as a slave (16) on the data bus (12) by means of a slave unit (36) that is part of the bus participant device (30), wherein the bus participant device (30) comprises a master unit (38) that can be activated. In particular, by means of the slave unit (36) and/or the master unit (38), a transmission of data telegrams (18) via the data bus (12) can be monitored for a malfunction of an active bus master (14). Preferably, subject to a result of the monitoring process, an activation of the master unit (38) by means of the slave unit (36) or the master unit (38) can be effected. The invention further relates to a method for operating a serial data bus (12), and to various safety-critical devices.

Abstract: In one embodiment, a computer-implemented method includes assigning a time budget to each of a plurality of virtual functions in a single-root input/output (SRIOV) environment, where a first time budget of a first virtual function indicates a quantity of cycles on an engine of the SRIOV environment allowed to the first virtual function within a time slice. A plurality of requests issued by the plurality of virtual functions are selected by a computer processor, where the selecting excludes requests issued by virtual functions that have used their associated time budgets of cycles in a current time slice. The selected plurality of requests are delivered to the engine for processing. The time budgets of the virtual functions are reset and a new time slice begins, at the end of the current time slice.

Abstract: According to one embodiment, a method for queuing a transaction request. The method may include receiving, by a processor, at least one transaction request from a transaction processing system. The method may also include storing the at least one received transaction request in a queue within a 64-bit storage system. The method may further include monitoring a 31-bit storage system. The method may also include determining at least one control block within the monitored 31-bit storage system is available. The method may further include transmitting the at least one stored transaction request to the monitored 31-bit storage system.

Abstract: An embedded port of a host bus adapter of a storage controller receives, from a driver of the host bus adapter, a first set of commands to quiesce I/O operations in the embedded port for a first period, wherein hardware resets of buses and other logic to which the embedded port is connected are performed in the first period of quiescing of I/O operations. One or more commands are received to resume selected I/O operations in the embedded port. A second set of commands is received to quiesce I/O operations for a second period. A command is received to allow normal I/O operations, subsequent to the driver being reinitialized during the second period of quiescing of I/O operations.

Abstract: Described are techniques for automatically configuring target port settings. A set of target port settings of a target port of a data storage system is initialized in accordance with a first target port setting configuration. It is determined whether the data storage system supports host registration. If the data storage system supports host registration, first processing is performed that includes registering a first host with the data storage system, wherein registering includes sending first information from the first host to the data storage system, the first information being sent from an initiator port of the first host to the target port; determining, using the first information, whether the set of target port settings of the target port require modification for use by the first host; and modifying the set of target port settings in accordance with the first information if the set of target port settings require modification.

Abstract: An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.

Abstract: Embodiments of the invention are directed toward systems and methods that execute legacy semiconductor applications using a non-legacy controller. In some embodiments a hardware abstraction layer and/or an emulator can be used to provide communication between a non-legacy operating system and legacy components including legacy applications. In some embodiments various methods and/or devices can be used to emulate and/or translate communications between legacy and non-legacy components.

Abstract: Full-AC load flow constitutes a core computation in power system analysis. A performance gain with a hardware implementation of a sparse-linear solver using a Field Programmable Gate Array (FPGA) is achieved by use of a DC network emulation of the power system bus. Analog Behavioral Models (ABMs) are used in an efficient strategy for designing analog emulation engines for large-scale power system computation. A generator model is also developed using analog circuits for load flow emulation for power system analysis to reduce computation time. The generator model includes reconfigurable parameters using operational transconductance amplifiers (OTAs). The circuit module is used with other reconfigurable circuits, i.e., transmission lines and loads.

Abstract: A computing device includes at least one master unit; at least one slave unit; an interconnect structure configured to route transactions from the at least one master unit to the at least one slave unit; and a transaction logger device configured to intercept and save a record of outstanding transactions sent by the at least one master unit to the interconnect structure. The transaction logger device is further configured to preserve the record of outstanding transactions when at least a part of the computing device is restarted.

Abstract: A communication system of the present disclosure includes a communication device that is communicatively coupled to a peripheral device. The peripheral device selects a selectable impedance from among multiple selectable impedances to communicate peripheral device information to the communication device. The communication device operates in an acquisition mode of operation to determine the selectable impedance to recover the peripheral device information. Optionally, the communication device can transition to a response mode of operation to respond to the peripheral device information.

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Abstract: Implementations of encoding techniques are disclosed. In one embodiment, an encoding system includes a codec device, a switching network, a rerouting circuit, a logic integrated circuit, and memory devices. The codec device includes a plurality of input and output (I/O) ports to transport data signals. The switching network is coupled both to the plurality of I/O ports and to a plurality of channels external to the device. The plurality of I/O ports includes at least one spare channel. The rerouting circuitry is coupled to and configured to control the switching network and the logic integrated circuit has logic circuity including command and decode queueing circuitry, redundancy circuits, and error correction circuitry. The memory devices do include any circuitry included in the logic circuitry. Other systems and apparatuses are also described.

Abstract: A method for configuring a high-speed serial bus parameter, including sending an application signal from a transmit end of a high-speed serial bus to a receive end of the high-speed serial bus, searching a parameter configuration table for a high-speed serial bus parameter that matches all of a frequency of the application signal, a loss of the application signal on the high-speed serial bus, and a material type of a wiring board of the high-speed serial bus, and configuring the high-speed serial bus according to the high-speed serial bus parameter. According to the method, a problem involving configuration of a high-speed serial bus parameter when a transmitted signal is compensated may be solved.

Abstract: An increase in the number of signal lines of a control apparatus for controlling devices of an automobile can be prevented and safety of the automobile can be secured. An in-vehicle communication system includes an input DHM that obtains device data from an input device, a BCM that generates control data for controlling an output device based on a value of the device data, and an output DHM that controls the output device according to the control data. The input DHM is composed of duplexed input control blocks, duplexed input shared memories, and an input NW control block. The BCM is composed of a BCM_NW control block, duplexed BCM shared memories for different intended uses, and duplexed arithmetic blocks. The output DHM is composed of an output NW control block, duplexed output shared memories, duplexed output control blocks, and a matching circuit.