Abstract: According to various embodiments, apparatuses and methods to communicate buffer allocation information are presented. The disclosed apparatuses and methods may include transmitting a buffer message by a wireless USB device to a wireless USB host, which may indicate an available storage space in a buffer of the USB device to store data from the USB host. The buffer message may be transmitted independent of whether or not the USB device has received a request message (e.g., from the USB host) for information relating the available storage space in the buffer. Additionally, the buffer message may be transmitted independent of any data exchange mechanism between the USB host and the USB device. The USB device may receive a data packet from the USB host, and transmit a data packet acknowledgement message including data packet status information, and information regarding the available storage space in the buffer.

Abstract: A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.

Abstract: Embodiments discussed herein refer to systems, methods, and circuits for conforming to power up sequencing rules of a conventional hard-wired data connection even though the hard-wired data connection that would ordinarily exist between two data controllers has been replaced with one or more contactless connectors. A consequence of replacing the hard-wired connection with a contactless connector is that the data controllers no longer directly control the power sequencing between the controllers because they are not able to directly communicate with each other over the hard-wired data connections. Power sequence assist circuitry may be used to assists the data controllers in establishing a link in accordance with the power sequencing rules of a particular wired interface despite the intentionally broken hard-wired data connection between the two controllers by instructing the contactless connectors to communicate with their respective data controllers in compliance with the power sequencing rules.

Abstract: A transmission apparatus includes a logic circuit for performing a predetermined process, and outputting a logic output signal depending on the process, an open-drain signal generation circuit, connectable at an input terminal to the logic circuit and at an output terminal to a pull-up resistor, and a transmission path failure determination circuit for determining whether there is a failure in a transmission path which transmits a signal outputted from the logic circuit via the open-drain signal generation circuit, wherein the transmission path failure determination circuit includes an edge waveform information obtaining circuit for obtaining edge waveform information indicating a waveform of at least one of a rising edge and a falling edge of an application signal, and a failure determination circuit for determining whether the edge waveform information satisfies a predetermined condition, and outputting a failure signal indicating that there is a failure in the transmission path.

Abstract: A method and an information handling system provide flexible interconnections between two endpoints and in particular to allow for the allocation and reallocation of PCI lanes. A flexible interconnect media system is capable of connecting a CPU to an I/O device. The flexible interconnect media system includes I/O slots that are each capable of receiving an I/O device, connection interfaces each correlated with an I/O slot, link taps with correlated ports for each CPU, and flexible interconnect media capable of connecting an open connection interface with an open link tap, whereby a connection between the CPU and the I/O device is completed.

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

Abstract: A system may include a data acquisition hardware device (DAQ) for acquiring sample data and/or generating control signals, and a host system with memory that may store data samples and information associated with the DAQ and host system operations. The DAQ may push hardware status information to host memory, triggered by predetermined events taking place in the DAQ, e.g. timing events or interrupts. The DAQ may update dedicated buffers in host memory with status data for any of these events. The pushed status information may be read in a manner that allows detection of race conditions, and may be used to handle data acquisition, output control signaling, and interrupts as required without the host system having to query the DAQ. The DAQ may also detect data timing errors and report those data timing errors back to the host system, and also provide improved output operations using counters.

Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

Abstract: A communication interface includes one or more input/output circuitries, each input/output circuitry including a pointer generation block that controls write pointers of a respective input/output circuitry and read pointers of the respective input/output circuitry. Each input/output circuitry also includes input/output buffers communicatively coupled to the pointer generation block. Each input/output circuitry further includes a receive delay-locked loop that provides a clock signal to the plurality of input/output buffers. Each input/output circuitry also includes one or more transmit delay-locked loops that delay the clock signal.

Abstract: In a system and method for providing UI-to-UI asynchronous communication, a bridge is coupled to an asynchronous channel based bus that has at least one Galactic channel. The bridge receives each message on the Galactic channel, and converts each message from a channel message format used by the Galactic channel to a common message format. The bridge utilizes a socket to broadcast each converted message to, and receive messages from, the one or more other bridges. The bridge determines that a message received from the one or more other bridges is destined for the Galactic channel. The bridge converts the message into the channel message format used by the Galactic channel. The bridge distributes the converted message to the at least one Galactic channel.

Abstract: An electronic device controller, in order to link various electronic devices without requiring troublesome installation of applications, drivers, etc.

Abstract: Creating, maintaining and using a lock dependency graph in a way that includes the following steps: (i) acquiring a first restriction on processor access in a multi-processor computer system; (ii) modeling the first restriction as first locking primitive information; and (iii) storing data corresponding to the first locking primitive information in a lock dependency graph. The first restriction on processor access is one of the following two types: (i) disabling the interrupts on a given processor; and/or (ii) sending inter-processor interrupts with synchronous waiting from one processor to another (including itself).

Abstract: In a system and method for providing UI-to-UI asynchronous communication, a bridge is coupled to an asynchronous channel based bus that has at least one Galactic channel. The bridge receives each message on the Galactic channel, and converts each message from a channel message format used by the Galactic channel to a common message format. The bridge utilizes a socket to broadcast each converted message to, and receive messages from, the one or more other bridges. The bridge determines that a message received from the one or more other bridges is destined for the Galactic channel. The bridge converts the message into the channel message format used by the Galactic channel. The bridge distributes the converted message to the at least one Galactic channel.

Abstract: A method performed by an information handling system, the method including bifurcating, by a processor of the information handling system, an I/O unit (IO unit) of the information handling system into a first root port and a second root port, wherein the first root port comprises a first pre-determined number of first lanes of the IO unit and the second root port comprises the first pre-determined number of second lanes of the IO unit. The method further including discovering, by the processor, a first I/O device (IO device) coupled to the IO unit, wherein the first IO device utilizes a first lane width that is greater than the first pre-determined number of lanes, and in response to discovering the first IO device, bifurcating, by the processor, the IO unit into a third root port, wherein the third root port comprises the first lanes and the second lanes.

Abstract: Provided is a shared resource access arbitration method of a shared resource access arbitration apparatus, the shared resource access arbitration method including: receiving, from at least one master apparatus, buffer status information related to a buffer included in the at least one master apparatus; determining, based on the received buffer status information, priorities of shared resource access requests received from a plurality of master apparatuses including the at least one master apparatus; and granting, according to the determined priorities of the shared resource access requests, one of the shared resource access requests having a high priority.

Abstract: A modular assembly of a module for a Logic Controller, including a container and a cartridge. The cartridge has a first electrical interface part and an electronic circuit arranged to provide a predetermined electronic function. The container has a housing, a backplane connector, a terminal connector and a receptacle extending inside the housing and adapted to receive the cartridge. The receptacle includes a second electrical interface part adapted to connect with the first electrical interface part. The cartridge and the receptacle are arranged to electrically connect the first and second electrical interface parts to establish an electrical interface when the cartridge is removably inserted in the receptacle of the container. The housing of the container defines the mechanical form factor of the module, while the cartridge determines the electronic functionality of the module. Accordingly, multiple containers having different form factors may accommodate the same cartridge.

Abstract: Apparatuses and methods for providing and interpreting command packets for the direct control of non-volatile memory channels within a solid state drive are disclosed herein. An example apparatus may include a plurality of flash memories configured into a plurality of channels and a controller coupled to the plurality of flash memories.

Abstract: A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

Abstract: Embodiments of the invention are directed toward systems and methods that execute legacy semiconductor applications using a non-legacy controller. In some embodiments a hardware abstraction layer and/or an emulator can be used to provide communication between a non-legacy operating system and legacy components including legacy applications. In some embodiments various methods and/or devices can be used to emulate and/or translate communications between legacy and non-legacy components.

Abstract: An apparatus comprises a positive data input/output terminal configured to be connected with a positive data line of a USB device, wherein the positive data input/output port is weakly pulled up to a first voltage potential through a pull-up resistor, a negative data input/output terminal configured to be connected with a negative data line of the USB device, wherein the negative data input/output terminal is connected to a second voltage potential, a window comparator having an input detecting a voltage across the two data input/output terminals and a wake-up signal generator connected to an output of the window comparator, wherein the wake-up signal generator is configured to generate a signal for adjusting a switching frequency of a power converter after the USB device is connected to the power converter.