Abstract: A semiconductor device includes a burst control circuit configured to generate burst information depending on a logic level of a setting bit when an operation setting signal is inputted and configured to generate a burst control signal from the burst information in the case where a read signal is inputted. The semiconductor device also includes a data processing circuit configured to output output data by performing first and second burst operations for internal data, depending on a logic level of the burst control signal.

Abstract: In one embodiment, a heterogeneous integrated solid state drive includes a plurality of solid state memory devices including at least one solid state memory device of a first type and at least one solid state memory device of a second type, a controller coupled to each of the plurality of solid state memory devices and an interface coupled to the controller. The controller is configured to receive at least one user-defined memory parameter and to create at least one namespace satisfying the at least one user-defined memory parameter in at least one of the plurality of solid state memory devices. In one embodiment, the at least one user-defined memory parameter is one of a group consisting of a capacity, a quality of service level, an assured number of I/O operations per second, a bandwidth, a latency, and an endurance.

Abstract: An apparatus in one embodiment comprises a storage system including multiple storage nodes each having a plurality of storage devices. Each of the storage nodes further comprises a set of processing modules configured to communicate with corresponding sets of processing modules on other ones of the storage nodes. The sets of processing modules of the storage nodes collectively comprise at least a portion of a distributed storage controller of the storage system. The distributed storage controller is configured to implement token-based data flow control between designated ones of the modules by determining a token distribution for the designated modules, the token distribution providing an allocation of tokens to particular ones of the designated modules. A given one of the modules is configured to limit its generation of messages to other modules based at least in part on availability of corresponding ones of the tokens allocated to the given module.

Abstract: A data processing system is disclosed, which relates to a technology for implementing a convergence memory system provided with a plurality of memories. The data processing system includes a compute blade configured to generate a write command to store data and a read command to read the data, and a memory blade configured to selectively performed read and write operations in response to the read and write commands in a plurality of memories. The compute blade has a memory that stores information about performance characteristics of each of the plurality of memories, and is configured to determine priority information through which eviction of a cache line is carried out based on the stored information.

Abstract: Systems and processes for managing memory compression security to mitigate security risks related to compressed memory page access are disclosed herein. A system for managing memory compression security includes a system memory and a memory manager. The system memory includes an uncompressed region configured to store a plurality of uncompressed memory pages and a compressed region configured to store a plurality of compressed memory pages. The memory manager identifies a memory page in the uncompressed region of the system memory as a candidate for compression and estimate a decompression time for a compressed version of the identified memory page. The memory manager determines whether the estimated decompression time is less than a constant decompression time. The memory manager, based on a determination that the estimated decompression time is less than the constant decompression time, compresses the memory page and writes the compressed memory page in the compressed region.

Abstract: This disclosure describes techniques for extending a range of bidirectional bus communications through the use of a differential signal path. The disclosed techniques include first separating the bidirectional bus into first and second unidirectional buses that transmit and receive signals, respectively, and then communicating the signals from the first and second unidirectional buses over a differential signal path. The separation of the bidirectional bus into the first and second unidirectional buses is performed using logic circuitry that blocks or permits communication between a given one of the first and second buses and the bidirectional bus based on whichever one of the first and second buses becomes dominant first. If the logic circuitry determines that the first bus becomes dominant before the second bus, the logic circuitry permits communications between the first bus and the bidirectional bus and blocks communications between the second bus and the bidirectional bus.

Abstract: A storage device for performing a garbage collection operation using a partial block erase operation includes: a memory device including a plurality of main blocks each including a plurality of sub-blocks; and a memory controller configured to perform a garbage collection operation for securing free blocks in which no data is stored, among the main blocks, wherein the memory controller includes a write handler configured to erase at least a portion of a target block, among the main blocks, according to whether an amount of valid data in at least one victim block exceeds a storage capacity of one main block.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. The computer system includes a service processor. The service processor monitors events of one or more ACPI compliant devices of a host of the service processor. The service processor maintains device data associated with the one or more ACPI compliant devices based on the events in a data store of the service processor. The service processor emulates an ACPI controller to monitor a communication channel for detecting one or more ACPI commands from the host. The service processor processes the device data in the data store in response to detecting the one or more ACPI commands on the communication channel.

Abstract: A processor includes, an engine that transmits a read command or the other command; and a command transfer unit that performs arbitration to select a command to be executed among the commands transmitted from the engines and outputs the command selected, wherein the command transfer unit that, in case that the read command is selected on the arbitration, brings a subsequent read command into the arbitration after a period represented an issue interval control value in relation to a data transfer length of the read command selected, the subsequent read command being transmitted from the engine which has transmitted the read command selected on the arbitration.

Abstract: An accessory device for an electronic protection relay comprising: a first communication port for communication with one or more electronic devices of the electronic protection relay or operatively connected with the electronic protection relay; a second communication port for communication with one or more computerized units through the Internet; a first processing means to manage the operation of the accessory device, the first processing means being operatively coupled with the first and second communication ports. The accessory device is configured to execute a data-gathering procedure (DGP), in which the accessory device polls one or more electronic devices, which are in communication with the accessory device through the first communication port, and receives grid data (D), which are related to the operation of an electric power distribution grid including the electronic protection relay, from the electronic devices in response to the polling.

Abstract: A semiconductor apparatus includes first transmitters allocated to a first data byte, and second transmitters allocated to a second data byte, wherein a power supply node of each transmitter allocated to a deactivated byte of the first data byte and the second data byte is coupled with a ground terminal.

Abstract: Methods and systems for dynamically controlling buffer size in a computing device in a computing device (“PCD”) are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

Abstract: This invention discloses a memory card access module and a memory card access method. The memory card access method is applied to an electronic device. A processing unit of the electronic device accesses a memory card through a memory card slot. The method includes steps of: detecting whether the memory card supports a Peripheral Component Interconnect Express (PCIe) interface; when the memory card does not support the PCIe interface, controlling the processing unit to access the memory card through a first data transmission path and performing data format conversion between a transmission interface and the PCIe interface using a memory card access unit disposed on the first data transmission path; and when the memory card supports the PCIe interface, controlling the processing unit to access the memory card through a second data transmission path that allows the processing unit and the memory card to transmit data through the PCIe interface.

Abstract: A firmware enumerates the buses of root bridges in the computing system. If an OOR condition occurs during enumeration of the buses, the firmware determines the number of required buses for each root bridge causing an OOR condition. The number of required buses for bridge devices connected to each root bridge causing an OOR condition can be identified using the same set of bus numbers. Once the firmware has determined the number of buses required by each root bridge, including those not causing an OOR condition, the firmware reallocates the number of available buses between the root bridges such that each root bridge is allocated a number of the available buses greater than or equal to the number of required buses. The firmware stores data identifying the allocation and restarts the computing device. Upon rebooting, the computing system utilizes the new allocation of bus numbers to eliminate the OOR condition.

Abstract: Disclosed is an electronic device including a first communication circuit that perform communication by using a first communication protocol, and a processor electrically connected to the first communication circuit, wherein the processor activates the first communication circuit based on a predetermined mutual operation, sets an operating mode of the electronic device based on at least part of the activation of the first communication circuit, and operates a universal serial bus (USB) host controller through a switching circuit based on the set operating mode.

Abstract: Methods, systems and computer program products for operating an output processor a transaction processing system are provided. Aspects include receiving a request by an output processor to deliver an output message having a plurality of message segments and obtaining a target buffer size. Aspects also include allocating an output buffer for the output message, the output buffer having the target buffer size and iteratively obtaining a message segment of the plurality of message segments and storing the message segment in the output buffer. Based on a determination that all of the plurality of message segments have been stored, aspects include delivering the output message. Based on a determination that the output buffer is full and that all of the plurality of message segments have not been stored in the output buffer, aspects further include increasing the target buffer size to a maximum buffer size.

Abstract: A system includes: a nonvolatile memory; a memory controller configured to control the nonvolatile memory, the memory controller including a first buffer memory for temporarily storing write data to be written to the nonvolatile memory; and a second buffer memory having a lower operational speed and a higher memory capacity than the first buffer memory. The memory controller is configured to transmit the write data from the first buffer memory to the second buffer memory and to the nonvolatile memory, and to release an operational state of the first buffer memory after transmitting the write data from the first buffer memory to the second buffer memory and to the nonvolatile memory. Writing additional write data to the first buffer memory is prohibited prior to the release of the operational state of the first buffer memory, and is permitted after the release of the operational state of the first buffer memory.

Abstract: A method for indicating a status of a storage device to be implemented by a complex programmable logic device (CPLD) is provided. The CPLD is coupled to a connector for connection with the storage device, and to an LED. The method includes: in response to receipt of a signal set from a connector, determining whether the connector is connected with a storage device based on the signal set; when affirmative, identifying the storage device based on the signal set; operating in a mode corresponding to a result of identification; generating a determination result representing an operating status of the storage device based on the signal set; and outputting a control signal corresponding to the determination result to the LED.

Abstract: A memory system includes: a non-volatile memory device for including a first storage region and a second storage region; and a controller for including first and second interfaces for inputting/outputting a data to/from a host, inputting/outputting a first data of the first storage region through the first interface, and inputting/outputting a second data of the second storage region through the second interface, wherein when the first data is programmed in the first storage region, the controller detects a value of the first data, selectively inverts the value of the first data based on the detection result, and program a resultant value, and when the second data is programmed in the second storage region, the controller detects a state of the second storage region where the second data is programmed, selectively inverts a value of the second data based on the state detection result, and program a resultant value.

Abstract: Embodiments discussed herein refer to systems, methods, and circuits for conforming to power up sequencing rules of a conventional hard-wired data connection even though the hard-wired data connection that would ordinarily exist between two data controllers has been replaced with one or more contactless connectors. A consequence of replacing the hard-wired connection with a contactless connector is that the data controllers no longer directly control the power sequencing between the controllers because they are not able to directly communicate with each other over the hard-wired data connections. Power sequence assist circuitry may be used to assists the data controllers in establishing a link in accordance with the power sequencing rules of a particular wired interface despite the intentionally broken hard-wired data connection between the two controllers by instructing the contactless connectors to communicate with their respective data controllers in compliance with the power sequencing rules.