Patents Examined by Ismail A Muse
  • Patent number: 11757062
    Abstract: A method for manufacturing a light emitting device includes: preparing a substrate having a first region and a second region surrounding the first region; mounting a plurality of light emitting elements in the first region; mounting a reinforcement member on the second region; forming and curing a sealing member in contact with the reinforcement member and with the light emitting elements, the sealing member having a lower rigidity than the reinforcement member; and cutting the substrate, the reinforcement member, and the sealing member to separate into individual light emitting devices each including one or more of the light emitting elements.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: September 12, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Yoichi Bando
  • Patent number: 11757080
    Abstract: The present invention relates to a multi-sided light-emitting circuit board, which includes: a transparent substrate layer and a first conductive circuit layer on at least one surface of the transparent substrate layer. The first conductive circuit layer includes conductive portions arranged at intervals. A metal piece is formed on a surface of each conductive portion away from the transparent substrate layer. An accommodation space is formed between adjacent metal pieces. The accommodation space is provided with a light-emitting chip. Each light-emitting chip includes two electrodes. The two electrodes are respectively located at opposite ends of the light-emitting chip. The electrodes are respectively electrically connected to adjacent metal pieces. An encapsulant layer is formed on a surface of the first conductive circuit layer. The encapsulant layer covers and encapsulates the metal pieces and the light-emitting chips.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 12, 2023
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Zu-Ai Li, Mei-Hua Huang, Jin-Cheng Wu, Si-Hong He, Ning Hou
  • Patent number: 11757249
    Abstract: A substrate for mounting a light-emitting element includes a substrate with a plate shape and a base that protrudes from a front surface of the substrate, wherein the base has a mounting part for mounting a light-emitting element on a top surface thereof and composes a sloping surface that slopes with respect to the front surface and the substrate and the base are integrally formed of a ceramic.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: September 12, 2023
    Assignee: KYOCERA Corporation
    Inventor: Youji Furukubo
  • Patent number: 11742457
    Abstract: The disclosure discloses a method for manufacturing light-emitting diode (LED) chips. The manufacturing method includes: providing a plurality of LED elements; randomly mixing the plurality of LED elements; performing a mesa process on the plurality of LED elements; and forming at least one pair of electrodes on the plurality of LED elements. An electronic device includes the LED chips.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: August 29, 2023
    Assignee: Innolux Corporation
    Inventors: Tsau-Hua Hsieh, Jian-Jung Shih, Tzu-Min Yan
  • Patent number: 11742368
    Abstract: An image sensing device is disclosed. The image sensing device includes a semiconductor substrate including an active region, a first impurity region and a second impurity region formed in the active region, a photoelectric conversion region disposed over the semiconductor substrate to be directly coupled to the first impurity region and configured to generate photocharges in response to incident light and transmit the generated photocharges to the first impurity region, a switching element disposed coupled to the first impurity region and the second impurity region and configured to transmit the photocharges stored in the first impurity region to the second impurity region, an insulation structure disposed on sides of the photoelectric conversion region and a plurality of conductive lines disposed in the insulation structure and configured to read out an electrical image signal corresponding to the photocharges generated by the photoelectric conversion region.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 29, 2023
    Assignee: SK hynix Inc.
    Inventor: Byoung Gyu Kim
  • Patent number: 11742334
    Abstract: A light emitting assembly includes a substrate, an adhesive layer on the substrate, and a plurality of light emitting units on the adhesive layer. Each of the light emitting units includes a first-type semiconductor layer, a second-type semiconductor layer, an active layer disposed between the first-type and second-type semiconductor layers, a first electrode electrically connected to the first-type semiconductor layer, and a second electrode electrically connected to the second-type semiconductor layer. A light emitting apparatus including the light emitting assembly is provided. Methods for making the light emitting assembly and the light emitting apparatus are provided.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 29, 2023
    Assignee: Xiamen San'An Optoelectronics Co., Ltd.
    Inventors: Tung-Kai Liu, Shao-Ying Ting, Chen-Ke Hsu, Chia-En Lee
  • Patent number: 11742341
    Abstract: A display device manufacturing method is provided including a display module in which an active area and a non-active area surrounding the active area are defined. A first hole is perforated having a first diameter on the active area. A second hole is formed having a second diameter by irradiating a laser area at least partially surrounding the first hole with a laser. The second diameter is larger than the first diameter.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Myungan Min
  • Patent number: 11735573
    Abstract: A slicing wafer includes a driver circuit substrate; a plurality of epitaxial layer slices arranged side-by-side on the driver circuit substrate; and a bonding layer, formed between the driver circuit substrate and the plurality of epitaxial layer slices.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: August 22, 2023
    Assignee: JADE BIRD DISPLAY (SHANGHAI) LIMITED
    Inventors: Qunchao Xu, Qiming Li
  • Patent number: 11735629
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a gate structure on the substrate. The semiconductor device includes a channel on the substrate. The semiconductor device includes a source/drain layer on the channel. Moreover, the semiconductor device includes a spacer on a sidewall of the gate structure. The spacer includes a central portion overlapping the channel in a vertical direction, and a protrusion portion protruding from the central portion. Related methods of manufacturing semiconductor devices are also provided.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 22, 2023
    Inventors: Seung-Min Song, Woo-Seok Park, Jung-Gil Yang, Geum-Jong Bae, Dong-Il Bae
  • Patent number: 11728225
    Abstract: Disclosed in the present specification are an apparatus and a method capable of quickly verifying a plurality of micro LEDs. An LED verification substrate according to the present specification is a micro LED verification substrate having a plurality of verification chips, wherein each verification chip can comprise: a first contact deposited on the upper side of a lower substrate; a first passivation layer deposited on the upper side of the first contact; a second contact deposited on the upper side of the first passivation layer; a second passivation layer deposited on the upper side of the second contact; a first bump electrically connected to the first contact and protruding above the upper surface of the second passivation layer; and a second bump electrically connected to the second contact and protruding above the upper surface of the second passivation layer.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: August 15, 2023
    Assignee: Research Cooperation Foundation of Yeungnam University
    Inventors: Si Hyun Park, Young Woong Lee
  • Patent number: 11710797
    Abstract: The present embodiments provide a transparent electrode having a laminate structure of: a metal oxide layer having an amorphous structure and electroconductivity, and a metal nanowire layer; and further comprising an auxiliary metal wiring. The auxiliary metal wiring covers a part of the metal nanowire layer or of the metal oxide layer, and is connected to the metal nanowire layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: July 25, 2023
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuyuki Naito, Naomi Shida, Mitsunaga Saito, Takeshi Niimoto
  • Patent number: 11705439
    Abstract: A multi-color LED display comprises pixels, each comprising a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel comprises a first light-emitting diode (LED) that emits a first color of light, the second sub-pixel comprises second LEDs that emit a second color of light different from the first color of light, and the third sub-pixel comprises third LEDs that emit a third color of light different from the first color of light and different from the second color of light. The second LEDs are electrically connected in parallel and the third LEDs are electrically connected in series.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 18, 2023
    Assignee: X Display Company Technology Limited
    Inventors: Matthew Alexander Meitl, Christopher Andrew Bower, Ronald S. Cok, Brook Raymond
  • Patent number: 11699728
    Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 11, 2023
    Inventors: Chang Woo Noh, Seung Min Song, Geum Jong Bae, Dong Il Bae
  • Patent number: 11696489
    Abstract: A flexible display apparatus comprises a glass substrate including a flat surface and a glass etching surface that is curved, and a flexible display panel including a bending portion on the glass etching surface.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: July 4, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SeungHan Paek, Seongwoo Park, Saemleenuri Lee
  • Patent number: 11688822
    Abstract: A pair of optical components is used in an isolator that enables electric isolation. Each of the optical components includes: first lens portions arranged on different optical paths and transmitting light in a first direction; second lens portions arranged on different optical paths and transmitting light in the second direction orthogonal to the first direction; and a reflection portion reflecting, in the second direction, the light in the first direction transmitted through the first lens portion and guiding the light to the second lens portion, or reflecting, in the first direction, the light in the second direction transmitted through the second lens portion and guiding the light to the first lens portion The second lens portion included in one of the pair of optical components and the second lens portion included in the other optical component are spaced apart from each other and face each other.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: June 27, 2023
    Assignee: ADVANCED PHOTONICS, INC.
    Inventors: Xueliang Song, Nozomu Sato
  • Patent number: 11672177
    Abstract: A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer contains at least a fourth organic compound whose HOMO level is lower than or equal to that of the second organic compound and a fifth organic compound whose HOMO level is higher than that of the second organic compound.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 6, 2023
    Inventors: Hiromi Seo, Satoshi Seo, Satoko Shitagaki
  • Patent number: 11664276
    Abstract: A semiconductor die includes a substrate having a semiconductor surface layer bon a front side with active circuitry including at last one transistor therein and a back side. The sidewall edges of the semiconductor die have at least one damage region pair including an angled damage feature region relative to a surface normal of the semiconductor die that is above a damage region that is more normal to the surface normal of the die as compared to the angled damage feature region.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 30, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Matthew John Sherbin, Michael Todd Wyant, Christopher Daniel Manack, Hiroyuki Sada, Shoichi Iriguchi, Genki Yano, Ming Zhu, Joseph O. Liu
  • Patent number: 11640956
    Abstract: A module-rotation LED dome belongs to the technical field of display screens and includes multiple display devices. Each display device includes 1st-4th light-emitting units. The second light-emitting unit is located beside the first light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the first light-emitting unit. The third light-emitting unit is located below the second light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the second light-emitting unit. The fourth light-emitting unit is located beside the third light-emitting unit and oriented with a clockwise rotation of 90 degrees relative to the third light-emitting unit. The 2nd-4th light-emitting units sequentially are rotated clockwise with 90 degrees, so that adjacent full-color LEDs in the 1st-4th light-emitting units cannot form adjacent LEDs of a same color, and there is no condition of appearing a bright blue line.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 2, 2023
    Assignee: SHENZHEN GALAXYPIXEL ELECTRONICS CO., LTD
    Inventors: Ligang Zhao, Guangming Song, Heng Zhan, Youhe Zhang, Lei Liang
  • Patent number: 11632112
    Abstract: An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: Ravi Prakash Gutala, Aravind Raghavendra Dasu, Sean R. Atsatt, Scott J. Weber
  • Patent number: 11626551
    Abstract: Additional “auxiliary” bumps are used to stabilize alignment and reduce slippage of dense arrays of interconnect bumps on opposing die during a bonding process. One example of auxiliary bumps are interdigitated bumps. Interdigitated bumps are more self-aligning and laterally stable because bumps do not meet head-to-head. Rather, the head of a bump on one die falls into the space between bumps on the other die. Another example of auxiliary bumps are nail bumps. In nail bumps, one bump is harder (the nail) and “drives” into the opposing softer bump during bonding. This constrains the lateral movement of the two bumps relative to each other and reduces lateral slippage. In some embodiments, the auxiliary bumps and interconnect bumps are formed in the same process, and also bonded in the same process.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 11, 2023
    Assignee: Tectus Corporation
    Inventors: Nachiket Raghunath Raravikar, Arnold Daguio, Kwong-Hin Henry Choy, Tigran Nshanian, Paul Scott Martin