Patents Examined by Ismail A Muse
  • Patent number: 11626287
    Abstract: A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: April 11, 2023
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Juntao Li
  • Patent number: 11621382
    Abstract: The present invention relates generally to an anodic oxide film for electric contact, to an optoelectronic display, and to a method of manufacturing the optoelectronic display. More particularly, the present invention relates to an anodic oxide film for electric contact to electrically connect an optical element and a substrate in a position therebetween, to an optoelectronic display, and to a method of manufacturing the optoelectronic display.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: April 4, 2023
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Dong Hyeok Seo
  • Patent number: 11610875
    Abstract: Disclosed is a light-emitting array structure having a substrate, a plurality of light-emitting pixel units, a plurality of first signal wires, a plurality of second signal wires, and an encapsulating layer. The light-emitting pixel units are arranged in array on the substrate. Each light-emitting pixel unit includes a driving chip, a first flat layer, a first redistribution layer, a second flat layer, a second redistribution layer, and a light-emitting diode. Each first signal wire is electrically connected to a corresponding one of the first redistribution layers and extends in a first direction. The second signal wires extend in a level different from the first signal wires. Each second signal wire is electrically connected to a corresponding one of the second redistribution layers and extends in a second direction different from the first direction. The encapsulating layer covers the light-emitting pixel units, the first and second signal wires, and the substrate.
    Type: Grant
    Filed: November 22, 2020
    Date of Patent: March 21, 2023
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jian-Chin Liang, Chien-Nan Yeh, Shih-Lun Lai, Jo-Hsiang Chen
  • Patent number: 11600756
    Abstract: A display device includes: a substrate including first areas and second areas alternately arranged in a first direction in a plane view; a first electrode and a second electrode on the substrate and spaced apart from each other in a second direction crossing the first direction; a first insulation layer on the substrate and covering the first electrode and the second electrode; and a light emitting element on the first insulation layer and electrically connected to the first electrode and the second electrode, the first insulation layer having a first thickness in the first area and a second thickness thicker than the first thickness in the second area, and the light emitting element being located in the first area.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: March 7, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Bae Kim, Ji Eun Lee, Chong Chul Chai
  • Patent number: 11594611
    Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
  • Patent number: 11581462
    Abstract: A display device includes a substrate, an interlayer insulating layer over the substrate, a metal layer over the interlayer insulating layer, and a light emitting element over the metal layer. The interlayer insulating layer includes a plurality of a first depressed portions. The metal layer includes a first region bonding to the light emitting element and a second region surrounding the first region. The second region, a plurality of second depressed portions is provided along the plurality of first depressed portions.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: February 14, 2023
    Assignee: Japan Display Inc.
    Inventor: Yasuhiro Kanaya
  • Patent number: 11581430
    Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 14, 2023
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: David Pritchard, Heng Yang, Hongru Ren, Neha Nayyar, Manjunatha Prabhu, Elizabeth Strehlow, Salvatore Cimino
  • Patent number: 11575067
    Abstract: A display substrate, a display apparatus, and a manufacturing method for the display substrate are provided. The display substrate includes: a substrate and a plurality of pixel units arranged in an array on the substrate; the pixel unit includes a light emitting diode, a connecting metal pattern, and a thin film transistor arranged in sequence along a direction away from the substrate; the connecting metal pattern is conductively connected to a top electrode of the light emitting diode; an active layer of the thin film transistor is insulated and spaced from the connecting metal pattern, and the drain of the thin film transistor is conductively connected to the connecting metal pattern.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: February 7, 2023
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhao Kang
  • Patent number: 11562991
    Abstract: A backplane, a manufacturing method thereof, a backlight module and a display panel are provided. The backplane includes a base substrate; a first conductive layer located on the base substrate and including a wire; a first protection layer located at a side of the first conductive layer facing away from the base substrate; a second conductive layer located on the first protection layer and including a conductive sub-layer, the conductive sub-layer penetrating the first protection layer to be connected with the wire; a second protection layer located at a side of the second conductive layer facing away from the base substrate; a micro light-emitting diode (LED) penetrating the second protection layer to be connected with the conductive sub-layer; and a metallic reflective layer, located on the second protection layer and configured to reflect light irradiated onto the metallic reflective layer from the micro LED.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: January 24, 2023
    Assignees: Hefei Xinsheng Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jing Wang, Dong Li, Weiwei Chu, Wenjie Xu
  • Patent number: 11552215
    Abstract: A method of manufacturing a display device includes: forming a first electrode on a substrate; forming an insulating layer on the substrate and on the first electrode; providing light emitting elements in the insulating layer, each of the light emitting elements having a long axis and a short axis crossing the long axis and being configured to emit light; aligning the light emitting elements such that one end of each of the light emitting elements faces the substrate and the long axis of each of the light emitting elements is arranged in a direction from the substrate toward the insulating layer; patterning the insulating layer to form an insulating pattern exposing another end of each of the light emitting elements; and forming a second electrode electrically connected to the exposed other end of each of the light emitting elements.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung Jin Lee, Jin Yeong Kim, Jin Taek Kim, Mi Jin Park, Sang Ho Park, Tae Hoon Yang
  • Patent number: 11552059
    Abstract: The present invention discloses an LED display screen layout method, including an LED display screen, wherein the LED display screen is formed by splicing a plurality of LED modules; each LED module includes four tricolored LED lamps; the four tricolored LED lamps form a square; and the four tricolored LED lamps are arranged in directions formed by sequentially rotating one of the tricolored LED lamps by 90 degrees. With such layout design, when the LED display screen is rotated, no blue line appears at neighboring borders of the LED modules, thus not influencing the display effect of the display screen.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: January 10, 2023
    Inventors: Ligang Zhao, Guangming Song, Youhe Zhang, Jie Zhou, Lei Liang
  • Patent number: 11538967
    Abstract: Disclosed is a display device. The display device includes: a light transmissive plate including a first front surface, a rear surface facing the first front surface, and a hole positioned behind the first front surface and connected to the rear surface; and a display film attached to the rear surface of the plate, in which the display film includes a light transmissive substrate having a second front surface attached to the plate, an electrode layer formed on the second front surface, and a light source electrically connected to the electrode layer, and the light source is positioned in the hole.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 27, 2022
    Assignee: LG ELECTRONICS INC.
    Inventors: Daewoon Hong, Sangtae Park, Myeongwook Bae, Jeongsik Choi
  • Patent number: 11538959
    Abstract: A method for repairing a display device, the display device including a plurality of inorganic light emitting elements arranged in a matrix and an insulator arranged around the plurality of inorganic light emitting elements, the method comprising steps of: detecting a defective inorganic light emitting element as the inorganic light emitting element having a defect; removing the insulator around the defective inorganic light emitting element while the defective inorganic light emitting element remains without being removed by irradiating the insulator around the defective inorganic light emitting element with irradiation light; and removing the defective inorganic light emitting element after the insulator therearound has been removed.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: December 27, 2022
    Assignee: Japan Display Inc.
    Inventor: Akihiro Ogawa
  • Patent number: 11532598
    Abstract: Provided is a semiconductor package structure including a first die having a first bonding structure thereon, a second die having a second bonding structure thereon, a metal circuit structure, and a first protective structure. The second die is bonded to the first die such that a first bonding dielectric layer of the first bonding structure contacts a second bonding dielectric layer of the second bonding structure. The metal circuit structure is disposed over a top surface of the second die. The first protective structure is disposed within the top surface of the second die, and sandwiched between the metal circuit structure and the second die.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Ming-Fa Chen
  • Patent number: 11527520
    Abstract: The present disclosure relates to a micro light emitting diode (LED) display device including a substrate having a plurality of thin film transistors thereon; a plurality of micro light emitting devices (LEDs) on an upper surface of the substrate, the micro LEDs each having a protecting film provided with a first contact hole to expose a portion of an upper surface of a corresponding micro LED; at least one insulating layer covering the micro LED, the insulating layer provided with a second contact hole to expose a portion of the upper surface of the corresponding micro LED; and a connection electrode in the first contact hole and the second contact hole configured to transfer signals to the micro LED, wherein the first contact hole is larger than the second contact hole.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 13, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Seong Hwan Ju, Hyeon Ho Son, Jin Yeong Kim, Jung Eun Son, Hanchul Park, Hyunwoo Kim
  • Patent number: 11515294
    Abstract: A micro light emitting diode (LED) transfer method includes: preparing a transfer substrate including a plurality of micro LEDs, the plurality of micro LEDs having electrodes disposed in a first direction and a second direction different from the first direction on the transfer substrate; sequentially transferring a first set of micro LEDs among the plurality of micro LEDs in block units from the transfer substrate to first regions of a target substrate; and sequentially transferring a second set of micro LEDs among the plurality of micro LEDs in block units from the transfer substrate to second regions of the target substrate, and in the sequential transferring of the second set of micro LEDs, the second set of micro LEDs transferred to the second regions are disposed in the same electrode direction as an electrode direction of the first set of micro LEDs transferred to the first regions.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ohjae Kwon, Jinmo Kang, Donghwan Kim, Yong Namkung, Seondeok Hwang
  • Patent number: 11515295
    Abstract: The application discloses a light-emitting device including a carrier which includes an insulating layer, an upper conductive layer formed on the insulating layer, a plurality of conducting vias passing through the insulating layer, and a lower conductive layer formed under the insulating layer; four light-emitting elements arranged in rows and columns flipped on the carrier; and a light-passing unit formed on the carrier and covering the four light-emitting elements; wherein each of the light-emitting elements including a first light-emitting bare die emitting a first dominant wavelength, a second light-emitting bare die emitting a second dominant wavelength, and a third light-emitting bare die emitting a third dominant wavelength; and wherein two adjacent first light-emitting bare die in a row has a first distance W1, two adjacent first light-emitting bare die in a column has a second distance W2, and W1 is the same as W2.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: November 29, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Tzu-Hsiang Wang
  • Patent number: 11508846
    Abstract: A ferroelectric memory device according to one embodiment includes a semiconductor substrate, a fin structure disposed on the semiconductor substrate and having a trench, the trench having a bottom surface and a sidewall surface; a ferroelectric layer disposed on the bottom surface and the sidewall surface of the trench; a plurality of resistor layers stacked vertically in the trench, each resistor layer of the plurality of resistor layers having a different electrical resistance; and a gate electrode layer electrically connected to the each resistor layer in the plurality of resistor layers. The plurality of resistor layers are disposed between the gate electrode layer and the ferroelectric layer.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: November 22, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyangkeun Yoo
  • Patent number: 11508889
    Abstract: A light-emitting device includes a carrier with a first surface and a second surface opposite to the first surface; and a light-emitting unit disposed on the first surface and configured to emit a light toward but not passing through the first surface. When emitting the light, the light-emitting device has a first light intensity above the first surface, and a second light intensity under the second surface, a ratio of the first light intensity to the second light intensity is in a range of 2˜9.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 22, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Chiu-Lin Yao, Shuo-Chieh Kan, Chun-Wei Lin, Been-Yu Liaw
  • Patent number: 11508700
    Abstract: Disclosed herein are display devices having a left projector and a right projector. According to certain embodiments, a display device includes a first display package having a first LED die, a second LED die, a third LED die, and a first backplane die that is electrically connected to the first LED die, the second LED die, and the third LED die. Each of the first LED die, the second LED die, and the third LED die is symmetric about a first plane that is parallel to an emission direction of the first LED die and perpendicular to a longitudinal direction of the first LED die. The first backplane die is symmetric about a second plane that is parallel to the emission direction of the first LED die and parallel to the longitudinal direction of the first LED die.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: November 22, 2022
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Rajendra D. Pendse