Abstract: The invention relates to a semiconductor component (100) comprising a semiconductor chip (10) configured as a wafer level package, a magnetic field sensor (11) being integrated into said semiconductor chip.

Abstract: Aspects of the disclosure include a semiconductor structure that includes a vertical fin structure having a top portion, a bottom portion, vertical side walls, a source area in contact with the vertical fin structure, a drain area in contact with the vertical fin structure, a plurality of spacers comprising a first oxide layer in contact with the source area, and a second oxide layer in contact with the drain area. The first oxide layer can have a thickness that is equal to a thickness of the second oxide layer.

Abstract: Fabricating a capacitor includes performing an oxide formation operation on a sheet of material. The oxide formation operation forms an anode metal oxide on an anode metal. A thermal compression is performed on the sheet of material after the oxide formation operation is performed. The thermal compression applies thermal energy to the sheet of material while applying pressure to the sheet of material. After the thermal compression, the capacitor is assembled such that at least one electrode in the capacitor includes at least a portion of the sheet of material.

Abstract: Some embodiments of the present disclosure provide a semiconductor structure, including a substrate and a regrowth region. The substrate is made of a first material with a first lattice constant, and the regrowth region is made of the first material and a second material, having a lattice constant different from the first lattice constant. The regrowth region is partially positioned in the substrate. The regrowth region has a “tip depth” measured vertically from a surface of the substrate to a widest vertex of the regrowth region, and the tip depth being less than 10 nm. The regrowth region further includes a top layer substantially made of the first material, and the top layer has substantially the first lattice constant.

Abstract: Techniques for integrating DC-DC power converters with other on-chip circuitry are provided. In one aspect, an integrated DC-DC power converter includes: a GaN transistor chip having at least one GaN switch formed thereon; an interposer chip, bonded to the GaN transistor chip, having at least one power driver transistor formed thereon; TSVs present in the interposer chip adjacent to the power driver transistor and which connect the power driver transistor to the GaN switch; and an on-chip magnetic inductor formed either on the GaN transistor chip or on the interposer chip. A method of forming a fully integrated DC-DC power converter is also provided.

Abstract: A film comprising a polymer compound and a low molecular weight compound having carrier transportability, wherein the content of the low molecular weight compound is 5 to 40 parts by mass with respect to 100 parts by mass of the sum of the polymer compound and the low molecular weight compound, the diffraction intensity A specified by the following measuring method A is 3 to 50, and the intensity ratio (A/B) of the diffraction intensity A specified by the following measuring method A to the diffraction intensity B specified by the following measuring method B is 30 or less: (Measuring method A) the diffraction intensity A is the maximum diffraction intensity in a range of scattering vector of 1 nm?1 to 5 nm?1 in a profile obtained by an Out-of plane measuring method using a film X-ray diffraction method; (Measuring method B) the diffraction intensity B is the maximum diffraction intensity in a range of scattering vector of 10 nm?1 to 21 nm?1 in a profile obtained by an In-plane measuring method using a film X

Abstract: A light emitting device includes a resin package including a first lead and a second lead. A light emitting element includes a first electrode disposed to face the first lead and having a first post electrode projecting toward the first lead in a first projecting direction with a height equal to or larger than 50 ?m and equal to or smaller than 150 ?m in the first projecting direction and a second electrode disposed to face the second lead and having a second post electrode projecting toward the second lead in a second projecting direction with a height equal to or larger than 50 ?m and equal to or smaller than 150 ?m in the second projecting direction. A first electrically conductive bonding member connects the first lead and the first post electrode. A second electrically conductive bonding member connects the second lead and the second post electrode.

Abstract: A composite substrate 10 includes a semiconductor substrate 12 and an insulating support substrate 14 that are laminated together. The support substrate 14 includes first and second substrates 14a and 14b made of the same material and bonded together with a strength that allows the first and second substrates 14a and 14b to be separated from each other with a blade. The semiconductor substrate 12 is laminated on a surface of the first substrate 14a opposite a surface thereof bonded to the second substrate 14b.

Abstract: The present invention relates to a light-emitting diode having enhanced liability. More particularly, a light-emitting diode has enhanced liability in a high-temperature and/or high humidity environment as well as in a room-temperature environment and can have decrease in light-emitting characteristics prevented. In addition, the present invention relates to a light-emitting diode comprising a structure which enables enhancing of light reflection and having enhanced light extraction efficiency by means of light reflection through the structure.

Abstract: Inside an IGBT using GaN or SiC, light having an energy of approximately 3 [eV] is generated. Therefore, defects are caused in the gate insulating film of the IGBT. Furthermore, the charge trapped at a deep level becomes excited and moves to the channel region, thereby causing the gate threshold voltage to fluctuate from the predetermined value. Provided is a semiconductor device including a normally-ON semiconductor element that includes a first semiconductor layer capable of conductivity modulation and a first gate electrode, but does not include a gate insulating film between the first gate electrode and the first semiconductor layer; and a normally-OFF semiconductor element that includes a second semiconductor layer, a second gate electrode, and a gate insulating film between the second semiconductor layer and the second gate electrode. The normally-ON semiconductor element and the normally-OFF semiconductor element are connected in series.

Abstract: A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.

Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.

Abstract: A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region.

Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.

Abstract: A semiconductor device manufacturing method, including: mounting substrates on a mounting table within a processing chamber along a rotation direction of the table; starting to supply a first-element-containing gas to a first region in the chamber along the rotation direction, while rotating the table and exhausting the processing chamber; starting to supply a second-element-containing gas to a second region in the chamber; starting to generate, by a plasma generating unit in the second region, plasma of the second-element-containing gas in the second region to have a first activity; and forming a thin film containing first and second elements on the substrates by rotating the table to cause the substrates to sequentially pass through the first and second regions in turn so that a first-element-containing layer is formed in the first region and is modified in the second region by generating plasma having a second activity higher than the first activity.

Abstract: A thin film transistor array substrate includes a bottom gate disposed on a substrate and a bottom gate insulating layer covering the bottom gate, a semiconductor oxide layer disposed on the bottom gate insulating layer and an etch blocking layer covering the semiconductor oxide layer and including a first via, a drain disposed on the etch blocking layer and contacting with the semiconductor oxide layer through the first via and an insulating protection layer covering the drain, a second via arranged in the insulating protection layer, the etch blocking layer and the bottom gate insulating layer, a top gate disposed on insulating protection layer and contacting with the bottom gate through the second via. A method for manufacturing the thin film transistor array substrate is also disclosed. The thin film transistor prevents the threshold voltage thereof from being drifted in a case of negative bias illumination stress (NBIS).

Abstract: To provide an oxide semiconductor with a novel structure. Such an oxide semiconductor is composed of an aggregation of a plurality of InGaZnO4 crystals each of which is larger than or equal to 1 nm and smaller than or equal to 3 nm, and in the oxide semiconductor, the plurality of InGaZnO4 crystals have no orientation. Alternatively, such an oxide semiconductor is such that a diffraction pattern like a halo pattern is observed by electron diffraction measurement performed by using an electron beam with a probe diameter larger than or equal to 300 nm, and that a diffraction pattern having a plurality of spots arranged circularly is observed by electron diffraction measurement performed by using an electron beam with a probe diameter larger than or equal to 1 nm and smaller than or equal to 30 nm.

Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.

Abstract: A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

Abstract: According to one aspect, the invention relates to an element for quantum photodetection of an incident radiation in a spectral band centered around a central wavelength ?0, having a front surface intended for receiving said radiation, and including: a stack of layers of semiconductor material forming a PN or PIN junction and including at least one layer made of an absorbent semiconductor material having a cut-off wavelength ?0>?0, the stack of layers of semiconductor material forming a resonant optical cavity; and a structure for coupling the incident radiation with the optical cavity such as to form a resonance at the central wavelength ?0 allowing the absorption of more than 80% in the layer of absorbent semiconductor material at said central wavelength, and an absence of resonance at the radiative wavelength ?rad, wherein the radiative wavelength ?rad is the wavelength for which, at operating temperature, the radiative recombination rate is the highest.