Abstract: Apparatus and method for testing a CDMA integrated circuit including a demodulator for correlating input data with one of a set of codes and a test data pattern generator for spreading input test data with one of the set of codes to form a spread test data and providing the spread test data to the demodulator. The set of codes may be combined with the input test data to generate a set of spread test data which are then fed to the various components of the CDMA chip for testing the various components. In one embodiment, each one of the set of codes comprises a scrambling code and a spreading code.

Abstract: A processor includes a calculator, a plurality of electronic fuses for storing secret data and reader for reading out the plurality of electronic fuses to determine the secret data. By storing the secret data, like for example a secret key for the identification of the processor or a chip card, respectively, in which the processor is arranged, in electronic fuses, a secure and efficient and simultaneously flexible way for introducing sensitive information into an integrated circuit is achieved.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: A method, system and computer program product for generating a coverage model to describe a testing scheme for a simulated system are described. In a preferred embodiment, a simulated system is tested with a testing simulation program. A simple event database is generated with the testing simulation program. Results of a checker analysis from the testing with the testing simulation program are obtained, and coverage data is created from a coverage model configuration file, the simple event database and the results of the checker analysis.

Abstract: An apparatus and method to check integrity when handling data. The method provides a storage array which includes a plurality of sectors. The method defines (N) data state identifiers and (N) parity state identifiers. The method receives a command to handle data, where that command designates a target sector. The method determines the data state identifier assigned to the target sector, determines the parity state identifier assigned to the target sector, and compares the data state identifier and the parity state identifier. If the method determines that the data state identifier and the parity state identifier are the same, the method performs the command to handle data. Alternatively, if the method determines that the data state identifier and the parity state identifier differ, the method generates an error message.

Abstract: A process initializes the state of an output memory circuit of a scan cell located at the boundary of a logic circuit within an integrated circuit. Data is scanned into an input memory circuit of the cell while maintaining the cell in a mode providing normal operation of the logic circuit. The cell is placed in a test mode that disables normal operation of the logic circuit. The data scanned into the input memory circuit is transferred into the output memory circuit simultaneous with the placing the cell in the test mode. A transmission gate between the logic circuit and the output memory circuit and a transmission gate between the input memory circuit and the output memory circuit effect the changes between normal operation and test modes.

Abstract: An apparatus that edits a test pattern used in a circuit function test includes a generator that generates a regular pattern that includes a plurality of unit patterns, by inserting a redundant pattern into a test pattern, and a pattern number reduction editor that defines the regular pattern as one unit pattern in the circuit function test.

Abstract: A channel encoding apparatus and method are provided in which part of the parity bits are set to erroneous bits, and full parity bits are created by correcting the erroneous bits using a channel decoding apparatus of a receiver in a communication system. In the channel encoding apparatus, in order to generate a coded bit stream by adding a parity bit stream to a message bit stream, a partial parity generator generates a partial parity bit stream as a part of the parity bit stream using the message bit stream, an erasure generator generates a bit stream having an erroneous value as the remaining part of the parity bit stream, and a decoder calculates the value of the parity bit stream by correcting the bit stream having the erroneous value using a parity-check matrix that determines the parity bit stream, the message bit stream, and the partial parity bit stream.

Abstract: The present invention provides a semiconductor integrated circuit having area efficiency and repair efficiency improved by sharing a redundant memory macro among a plurality of SRAM macros. Each of the plurality of memory macros includes a memory cell array connected to word lines and bit lines and a redundant circuit that replaces a defective bit line of the memory cell array to a normal bit line and a redundant bit line and outputs defect information to a redundant signal line. The redundant memory macro includes a redundant memory cell array connected to redundant word lines and the redundant bit line, and a first word line connection circuit that connects a word line corresponding to a memory macro to be repaired and disconnects a word line corresponding to a normal memory macro from the redundant word line.

Abstract: In one embodiment, an apparatus comprises a scan circuit including at least a first and a second clock domain and a scan chain having a first plurality of scan cells positioned in the first clock domain and a second plurality of scan cells positioned in the second clock domain. A scan clock source, coupled to the scan chain, generates a first scan clock signal to the first plurality of scan cells and a second scan clock signal to the second plurality of scan cells. The first and the second clock signals have an inverted relationship.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A system and method of using recursive cyclic redundancy check (CRC)+forward error correction (FEC) for enhancing the channel coding gain for a DVB-H receiver, and using a physical (PHY) Reed-Solomon (RS) decoder+FEC to achieve better coding gain. The system and method utilize a dual mode RS decoder (erasure mode and error mode) for FEC decoding. The PHY RS is used to provide smaller granularity for FEC. The system includes a cache memory management scheme for implementing the recursive CRC/RS+FEC in very large scale integrated circuit chip (VLSI) hardware.

Abstract: An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. If the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.

Abstract: A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” multiple incoming test values to remove intentionally introduced logic difference (e.g., inversion) with respect to one another. Result combining circuit (108) can logically combine output data values and provide a resulting sequence to a pattern sequence test circuit (110).

Abstract: In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.

Abstract: A plurality of input circuits and a plurality of output circuits are connected to form a Boundary Scan Path Chain (BSPC). Part or all of the existing I/O bus is used as a test bus. When a test target system such as a logic circuit is tested, data of the input circuits is circulated in the BSPC to set the initial state. After a system clock is activated, data of the input circuits is loaded into shift registers provided in the input circuits or data of the output circuits is loaded into shift registers provided in the output circuits. A shift clock is activated to extract the data of the input or output circuits through the BSPC. Enable data is circulated in the BSPC, and data of the output circuits is supplied to the test bus only when the enable data is active.

Abstract: The present invention provides a method and apparatus for efficiently loading values into scan and non-scan memory elements. First, the network used to distribute control signals to the memory elements is cleared. Second, the desired values are loaded into the scan memory elements. Third, the values from the scan memory elements are propagated to the non-scan memory elements.

Abstract: Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.

Abstract: A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output from each programmable logic component to a fixed logic component, examining the outputs, and determining a validated output from among the outputs. An architecture for mitigating logic upsets includes an input, a plurality of programmable logic components, and a fixed logic component. The input is provided to each of the programmable logic components. Each programmable logic components includes an encryption algorithm and a first majority voting logic, and processes the respective input to determine a respective output. The fixed logic component includes a second majority voting logic. The fixed logic component receives each respective output from the programmable logic components, examines the outputs, and determines a validated output.

Abstract: A method and apparatus are described for testing at least one critical data path in a design of a digital integrated circuit chip during a simulation of the design. A dedicated memory-bypass-enable signal is provided to a memory-bypass-logic circuit of the design during test modes of the simulation. Data content of a memory circuit within the critical data path is protected, using the dedicated memory-bypass-enable signal, during part of a path-delay test mode of the simulation. The memory circuit is also bypassed using the memory-bypass-enable signal during a memory-bypass test mode of the simulation.