Abstract: A sequential scan cell includes an input port for functional data and an input for scan test data. The input for scan test data is an input to a master scan flip-flop coupled to a slave scan flip-flop defining a scan test circuit. Such a scan test circuit is coupled to the functional circuit of the sequential scan cell such that the path for a functional signal is not through the scan test circuit, imparting no performance penalty to the functional signal. Scan test data is scanned in and out of the sequential cell by two non-overlapping scan clocks that are active only when system functional clocks are in an off state.

Abstract: An OSD multi cursor display method and apparatus are provided, wherein an OSD source transmits a plurality of OSD multi cursor display data to a display apparatus by giving each data a peculiar ID, said display apparatus stores the plurality of received OSD multi cursor display data in a memory, said OSD source transmits only an OSD multi cursor ID and display location information to said display apparatus, and said display apparatus reads an OSD multi cursor display data of a corresponding ID and displays the data on a screen at a given cursor display location. Since only a plurality of OSD multi cursor data is transmitted initially, and thereafter only the ID of the OSD multi cursor and the display location information are transmitted, the amount of data in transmission is reduced, the processing speed becomes faster, and an OSD multi cursor can be displayed smoothly on a screen.

Abstract: A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the first word in response to the respective bit-grade, and inserting one of the candidate words into each of a plurality of candidate sequences, so that each of the candidate sequences contains one of the candidate words. The method further includes adding subsequent words to the candidate sequences, the subsequent words consisting of a further candidate word derived from a further word in the input sequence, computing respective sequence parameters for the candidate sequences, based on a relation between the candidate words and the subsequent words in the candidate sequences, selecting one of the candidate sequences in response to the sequence parameters, and outputting one of the candidate words contained in the selected candidate sequence.

Abstract: Data is arranged to one block obtained after a CIRC process so that a predetermined data pattern is recorded into a predetermined portion on a disc. By tracing back an encoding step of a Cross-Interleave Reed-Solomon Code (CIRC), a layout of recording data of one block before the CIRC process for allowing the predetermined data pattern to be recorded into the predetermined portion is obtained. An error correcting process of a CD-ROM mode 1 is executed. If a position of a parity coincides with data for forming the predetermined data pattern, a value of user data of an encoding sequence to form the parity is changed. After error correction encoding of a CD-ROM is executed, encoding of the CIRC is executed to the recording data of one block.

Abstract: A method and apparatus for performing add-compare-select processing using carry-save arithmetic. Data compressors that operate based upon carry-save principles are utilized to render the correct result without requiring intermediate results to be resolved. Intermediate results are truncated to ensure that the dynamic range of the add-compare-select unit is not exceeded, whilst ensuring that the resolution of the intermediate results is not adversely affected. The computation of two competing paths is delayed and only the difference is computed directly, resulting in a reduction of the propagation path through the add-compare-select unit.

Abstract: Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. The prediction device needs not activate the traceback modules when making a successful prediction. In other words, no access to the path memories is required. The predicted bits decoded and outputted by the decoded bit registers are the decoded bits from the Viterbi decoder. Therefore, the prediction device saves much traceback and power consumption for decoding.

Abstract: A read control system and method for a memory device are provided. One embodiment of a system, among others, includes dump logic coupled to a data source, said dump logic configured to receive a first group of a defined slice of data and a second group of the defined slice of data; and a true dump bus and a complement dump bus configured in a wired-OR arrangement, said dump logic configured to drive the first group of data onto the true dump bus and the second group of data onto the complement dump bus.

Abstract: A method (700) and apparatus (600) are described for performing 2M?1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) in an Ultrawide Bandwidth (UWB) receiver for decoding a message sequence encoded according to a convolutional code. Contents of the track buffer are updated in accordance with Register Exchange and outputs from the track buffer can further be input to a voting unit (114) where a voting scheme can be applied and a decision rendered as to the originally transmitted message sequence.

Abstract: Apparatus, and an associated method, for recovering the informational content of an encoded data block. Data bursts are delivered to a receiver. A series of data bursts together include all of the informational content of the encoded data block. A detector detects delivery to the receiver of the data bursts. A determiner determines indicia associated with the communicated data. And, responsive thereto, the data is decoded, selectably utilizing fewer than all of the data bursts that form the encoded data block.

Abstract: A method and an arrangement for detecting a collision in a communication network, such as a WLAN, on which data are sent in frames of variable lengths separated by inter-frame spaces, each frame including a header and a data payload field where the header includes information of the length of the frame, is provided. The method comprises the steps of estimating a noise level (41; 41-42) of a frame, the header of which being read by a receiver, preferably using constellation error measurement, comparing the estimated noise level with a reference noise level value, and detecting a collision with another weaker frame depending on the outcome of the comparison.

Abstract: Memory devices having a normal mode of operation and a test mode of operation are useful in quality programs. The test mode of operation includes a data compression test mode having more than one level of compression. The time necessary to read and verify a repeating test pattern can be reduced as only a fraction of the words of the memory device need be read to determine the ability of the memory device to accurately write and store data values. Output is selectively disabled if a bit location for one word of a group of words has a data value differing from any remaining word of its group of words for a number of groups of words.

Abstract: An eFuse data alignment verification apparatus and method are provided. Alignment latches are provided in a series of latch units of a write scan chain and a logic unit is coupled to the alignment latches. A sequence of data that is scanned-into the series of latch units of the write scan chain preferably includes alignment data values. These alignment data values are placed in positions within the sequence of data that, if the sequence of data is properly scanned-into the series of latch units, cause the data values to be stored in the alignment latches. The logic unit receives data signals from the alignment latches and determines if the proper pattern of data values is stored in the alignment latches. If the proper pattern of data values is present in the alignment latches, then the data is aligned and a program enable signal is sent to the bank of eFuses.

Abstract: An ECC determining unit determines whether an error detected by using an ECC has been corrected. When the detected error has not been corrected, an equalizer output sequence transfer unit transfers an equalizer output sequence yk stored in an equalizer output sequence storage unit to a transfer data storage unit in a hard disk controller, so that a high-performance decoding unit (software) performs repetitive decoding, using the transferred equalizer output sequence yk.

Abstract: A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit; routing the test signal source to the logic circuit; and determining if the logic circuit is defective. According to an alternate embodiment, a method enables re-routing a path from a shift register to a lookup table to determine whether a lookup table is defective. According to a further alternate embodiment, a method enables localized routing to reduce the probability that a defect is a result of a routing defect.

Abstract: In one embodiment, the invention is directed to a zeroing circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The zeroing circuit comprises logic for zeroing out a specified number of most significant bits (“MSBs”) of a selected portion of the debug data based on a mask generated by a mask generator block. A selection control signal provided to the mask generator block is operable to be decoded to a particular mask.

Abstract: In relation to the built-in self-test circuit (BIST circuit) for testing CAM macros, the present invention is intended to provide a means to enable reduction in amount of materials as required for wiring channel region for signal distribution, buffer, FF, etc., and in number of LSI pins, and further, to facilitate mounting on chips. The data generators for CAM testing, inserted between the APG for RAMs and CAM macros, create data to write to the CAM macros by obtaining the address signals directly or by decoding the same signals. The APG is common to all the memory macros, and testing proper to each CAM can be carried out by changing over the operation of the inserted data generators by means of the control signal. The data generators are arranged in the proximity of the CAM macros, the circuits to be tested.

Abstract: A test head performs at-speed testing of high serial pin count gigabit per second (GBPS) devices. The test head includes a device under test (DUT) coupled to a first portion of the test head and a rider board coupled to the DUT. The rider board includes a first signal path including switching matrices coupled to the DUT, a second signal path including bit error rate testing (BERT) engines, each of the BERT engines being coupled to each other, corresponding ones of the switching matrices, and to the DUT, and a third signal path including Ethernet testing circuits coupled to the DUT. The BERT engines allow for routing of a test signal from any of the switching matrices to any other switching matrix (e.g., between non-adjacent switching matrices).

Abstract: The invention features a method including: (i) providing an interference signal S(t) from two beams directed along different paths, wherein the signal S(t) is indicative of changes in an optical path difference n{tilde over (L)}(t) between the different paths, where n is an average refractive index along the different paths, {tilde over (L)}(t) is a total physical path difference between the different paths, and t is time; (ii) providing one or more coefficients representative of one or more errors that cause the signal S(t) to deviate from an ideal expression of the form A1 cos(?Rt+?(t)+?1), where A1 and ?1 are constants, ?R is an angular frequency difference between the two beams before being directed along the different paths, and ?(t)=nk{tilde over (L)}(t), with k=2?/? and ? equal to a wavelength for the beams; (iii) calculating a linear combination of values of the signal S(t); and (iv) reducing the effect of the deviation of S(t) from the ideal expression on an estimate of {tilde over (L)}(t) using an e