Abstract: The invention includes providing a display by moving a colorant particle, having an electric charge, inside a channel of a body in a direction that is substantially parallel to a direction of extension of the channel and a direction of incoming illumination rays. The colorant particle can be moved between a position at a bottom of the channel and at a top of the channel by the force of an electric field generated by a charge at the bottom of the channel. The invention can be applied to an analog dot display as well as a digital dot display. The invention covers methods of manufacturing the displays discussed above. The invention is also not limited to covering displays, and also covers at least print media, wherein colorant particles are locked at appropriate locations within the channels, either temporarily or permanently.

Abstract: A method for reducing the number of transitions generated by an LFSR is introduced. The transition monitoring window monitors the number of transitions occurring as random patterns generated from an LFSR are applied to a scan chain, and, if the number of transitions exceeds a threshold value (“k-value”), all further transitions are suppressed. The transition monitoring window monitors the patterns entering the LFSR, incrementing a counter if a transition is detected. If a transition is detected just before the exit of a lowest stage of the LFSR the counter is decremented. The signal from the counter is compared with the k-value at every clock tick, and if the count is greater than the k-value, the vector most recently applied to the scan chain is re-applied to the scan chain; if it is less than the k-value, the output from the LFSR is applied to the scan chain.

Abstract: A device for checking a transmission line carrying a plurality of digital and/or analogue transmission channels is provided. The device includes a measurement block designed to evaluate performances, search for faults and determine the quality of the line and services transmitted through the said line. A system for measuring disturbances is also provided. The system measures disturbances in a transmission line firstly connecting a subscriber to a high speed server through an xDSL modem, and secondly to a switched telephone network.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of the first sets of tracks, defining individual test inputs to apply to the first end of each of the at least two of the first sets of tracks, determining an expected logic result for a selected logical combination of the individual test inputs, applying the individual test inputs to the first end of each of the at least two of the first sets of tracks, performing the selected logical combination on the second ends of the at least two of the first sets of tracks to generate an actual logic result, and flagging an error if the actual result is not identical with the expected logic result.

Abstract: A PHS terminal device has first and second checking mechanisms, first and second starting mechanisms, a first storing mechanism, first confirming mechanism, and processing mechanism. The first checking mechanism executes a first check to determine detection of a Unique Word when receiving a time slot and outputs a first interrupting signal upon detection. The first starting mechanism starts a first interrupting routine in response to the first interrupting signal. The first storing mechanism stores the first check result. The second checking mechanism executes a second check determining whether reception of the time slot is completed and outputs a second interrupting signal when reception of the time slot is completed, and the second starting mechanism starts a second interrupting routine in response. The first confirming mechanism confirms the first check result. The processing mechanism executes data processing of the time slot according to the confirmation result of the second interrupting routine.

Abstract: Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.

Abstract: A latch is provided for rapidly stabilizing a latching operation. The latch comprises a first latch circuit for latching a first signal in response to a first portion of a second signal to generate a first latch signal, and a latch error compensator for compensating a latch error in the first latch signal generated by the first latch circuit to generate a compensated latch signal.

Abstract: Setting a minimum operating voltage (Vcc min) of the cache to a voltage value at which the number of cells that fail in the cache is between approximately 0.1% and approximately 1% of the number of lines in the cache, while the remaining cells continue to function correctly at the voltage value chosen for Vcc min, and compensating for errors produced by memory cells in the cache that fail when operated at the voltage value chosen for Vcc min.

Abstract: A system-on-chip (SOC) having built-in-self-test (BIST) circuits and a self-test method of the SOC are provided. The SOC having the BIST circuits includes intellectual property (IP) blocks having BIST logic circuits and a BIST control unit. The BIST logic circuit operates in a normal or a test mode in response to control data received through a system bus, and outputs test result data in the test mode. The BIST control unit tests the IP blocks by transferring the control data, a command signal, test pattern data, and test address signals to the BIST logic circuit through the system bus, and compresses and stores the test result data received through the system bus in the test mode.

Abstract: A data detection and decoding system in which a single parity bit added to the end of each code word by the encoder is used in the channel detector to improve the accuracy with which bit decisions are made in the channel detector. The bit estimates and the reliability estimates are then processed by the decoder to recover the original input bits. By using single parity for this dual purpose in combination with a decoder that follows the channel detector and uses the bit estimates and reliability estimates to recover the original input bits, performance of the data detection and decoding system is greatly improved while also overcoming the disadvantages of known digital recording systems.

Abstract: A test interface is configured to connect to a testing device and a communications device. The communications device may be configured to receive a data signal (that includes a desired data portion) from the test machine. The interface may include a data capture device and a buffer. The data capture device may be configured to receive a framing pulse signal from the communications device, to receive a framing pulse enable signal from the testing device, and to generate a reset signal in response to receiving the framing pulse signal and the framing pulse enable signal. The buffer may be configured to store the data signal from the communications device, and to clear all stored data in the buffer and store the desired data portion in response to receiving the reset signal.

Abstract: A data communication system has a combiner circuit that combines a set of information symbols with error correction codes and that generates a set of product codes that are at least three dimensional. A communication channel receives the set of product codes and provides the set of product codes with errors after a channel delay. A channel detector receives the set of product codes with the errors and generates a channel detector output. An error correction circuit receives the channel detector output and iteratively removes the errors to provide a set of reproduced information symbols with a reduced number of the errors.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device such as a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the automated testing procedure terminates, and the programmed IC begins to function according to the user design as determined by the last programmed bitstream.

Abstract: Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.

Abstract: Data structures and related methods facilitate processing of media content for a user-defined development project. In one embodiment, a data structure comprises a chain identified field for holding identifiers for identifying chains of components that are to be employed in connection with the development project, a source identifier field for denoting a project source associated with a particular chain identifier, a project time field for denoting when, during project execution, an associated source chain is required, a source time field for denoting which portion of a source is required to support execution of the project for an associated entry in the project time field, and a dependencies field for denoting whether an associated chain is dependent on any other chain(s).

Abstract: A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of data may be conveyed to the receiver serially via respective single-bit lanes. The segment of data, the redundant information, and the error detecting code may be accumulated within the receiver over a plurality of clock cycles. The receiver may detect an error in the segment of data using the error detecting code. In addition, the receiver may, in response to detecting the error, regenerate the segment of data using the redundant information. Further, the receiver may determine whether a resulting regenerated bit, along with remaining bits, of the segment of data are correct using the error detecting code.

Abstract: A built in self test (BIST) circuit is provided for a programmable logic device (PLD) constructed from fixed or hard core logic that includes circuitry to write recurring patterns of bits in the configuration memory in a frame by frame manner and read the cell state to enable the validation of every configuration bit at power up. The BIST circuitry can further be used to program the recurring patterns into the configuration memory, and then read frames of the configuration memory to detect the occurrence of single event upsets (SEU) that corrupt data in the configuration memory. The recurring patterns programmed do not require time consuming functional configuration of the PLD, and can be done in a production environment after power up without knowledge of how the PLD will later be configured. No soft logic is needed to form the BIST circuit, enabling 100% test coverage of the programmable configuration memory cells.