Abstract: A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

Abstract: Techniques are provided for capturing external signals at output pins on a programmable logic integrated circuit (IC) during a boundary scan test. A JTAG sample signal is routed to an input/output block on a chip and active during a JTAG sampling phase. An input buffer coupled to an output pin is turned on during the JTAG sample phase. Logic gates enable the input buffer in response to the JTAG sample signal so that the input buffer can capture a signal on the pin. The input buffer is turned off after the JTAG sampling phase to conserve power. The output buffer coupled to the pin that receives the test signal is tristated to prevent contention during the JTAG sampling phase. The techniques of the present invention can be used to test board level interconnects in less time and are easy to implement.

Abstract: In one embodiment, a method may include generating a test code segment including a number of selected opcodes and executing the test code segment for a plurality of iterations. The method may also include saving a first test result of the execution of the test code segment after a first iteration and comparing additional test results of each subsequent iteration with the first test result. The method may further include determining whether any of the additional test results are different than the first test result.

Abstract: A Maximum Likelihood Sequence Estimation (MLSE) decoder that decodes an encoded sequence of data symbols includes a branch metric unit for computing branch metrics for each trellis stage of the encoded sequence, a path metric unit for computing a path metric for each trellis stage using the computed branch metrics, and an M-at-a-time traceback unit for performing an M-at-a-time traceback operation using the computed path metrics. The M-at-a-time traceback operation generates M decoded data symbols in a single M-at-a-time traceback operation.

Abstract: Systems and methods for adaptively compressing test data are disclosed. One such method comprises the steps of examining a test data file that includes a first plurality of data units corresponding to a first plurality of DUT pins and a second plurality of data units corresponding to a second plurality of DUT pins, compressing the first plurality of data units using a first compression technique, and compressing the second plurality of data units using a second compression technique.

Abstract: A method for error detection and correction comprising performing a first modulation error scan of said modulation symbol, marking data that fails to comply with a predetermined criteria, demodulating said modulation symbols, computing a first error syndrome using said demodulated symbols, and correcting errors using said error syndrome computation.

Abstract: Disclosed are systems and methods of producing electronic devices. These electronic devices include excess circuits to be used as replacements for circuits that are found to be defective within the electronic device. The excess circuits are included in a different device component than the circuits that are found to be defective. The replacement process occurs after the excess circuits and defective circuits are included in an electronic device including the different device components. Identification of the defective circuits may occur before or after the defective circuits are incorporated in the electronic device. In some embodiments, systems and methods of the invention result in improved manufacturing yields as compared with the prior art.

Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.

Abstract: A mechanism for use with a bus provided from parallel, capacitively-coupled bus lines to restrict a number of possible transitions on the bus to a number that is smaller than the maximum number of possible transitions so that data transmissions on the bus occur at a transmission rate which is higher than the transmission rate allowable if the number of transitions had not been restricted.

Abstract: A binary latch that operates as an edge-triggered flip-flop and which is LSSD-testable that comprises an edge triggered master. The binary latch comprises an edge triggered master flip-flop (2), with a clock input connected to the system clock (SYS_CLK), with a data input (DI) and with an output (DO), a level sensitive scan design (LSSD) slave latch (3), connected to the output (DO) of the master flip-flop (2), a NAND gate (4) with a first input (41) connected to the system clock (SYS_CLK), a second input (42) connected to a test input (TEST) and with an output (43) connected to the LSSD slave latch clock input (LSSD_clk).

Abstract: Amplifying magnitude metric of received signals during iterative decoding of LDPC code and LDPC coded modulation. By appropriately selecting a metric coefficient value that is used to calculate the initial conditions when decoding LDPC coded signals, a significant reduction in BER may be achieved at certain SNRs. The appropriate selection of the metric coefficient value may be performed depending on the particular SNR at which a communication system is operating. By adjusting this metric coefficient value according to the given LDPC code, modulation, and noise variance, the overall performance of the decoding may be significantly improved. The convergence speed is slowed down so that the decoder will not go to the wrong codeword, and the moving range of the outputs of the decoder is restricted so that the output will not oscillate too much and will eventually move to the correct codeword.

Abstract: A storage technology for improving reliability in writing host data to a storage device is provided. A first check code based on write data is stored in cache memory 370, and storage section 50 is instructed to write, in specified predetermined storage area, write data with the first check code appended thereto, after which the storage section 50 is instructed to read data stored in said predetermined storage area; a second check code is generated on the basis of the read data, and in the event that the correspondence relationship between the first and second check codes is correct, it is decided that the write data was written normally to the storage section 50.

Abstract: A first interleaved address generator is configured to generate a first interleaved address, and a second interleaved address generator is configured to generate a second interleaved address substantially concurrently with the first interleaved address generator generating the first interleaved address. A controller is configured to disable the second interleaved address generator from generating the second interleaved address if the second interleaved address is not needed to produce a continuous stream of interleaved addresses.

Abstract: Memory array repair where the repair logic cannot operate at the same operating condition as the memory array is presented. In one embodiment, a test is run with the memory array configured in a first operating condition that repair logic for the memory array cannot achieve, and test data is accumulated from the test in the memory array. The memory array is then read with the memory array configured in a second operating condition that the repair logic can achieve using the test data from the test at the first operating condition. As a result, repairs can be achieved even though the repair logic is incapable of operating at the same condition as the memory array. A method, test unit and integrated circuit implementing the testing are presented.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: A system for efficiently utilizing a transmission capacity without complicated processing a hierarchical code comprised of a plurality of layers having different error correcting capabilities. In a transmitter, an encoding unit encodes an image in accordance with a hierarchical coding scheme to generate a plurality of layer data. An error correcting code addition unit performs error correction coding on each of at least one layer data including the lowermost layer data in accordance with an error correction coding scheme which gives higher error correcting capabilities to a lower layer than a higher layer. A transmission unit transmits each of the layer data and error correcting codes onto a transmission path. A receiver corrects possible errors introduced on the path into the layer data received from the transmitter according to the error correction coding scheme, and decodes layer data received in a quality available for decoding to restore the image.

Abstract: Methods and apparatus are provided that allow an electronic system having a signaling bus with a fault on a signaling conductor to operate at a degraded performance. A block of data is transferred from a first electronic unit to a second electronic unit over the signaling bus. A transmission sequence sends the block of data using all of the nonfaulty signaling conductors using a minimum number of beats required to complete the transmission.

Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.

Abstract: A computer process establishes data frequencies for recording data in zones of a zone bit recording medium in a disc drive. At least three data points are identified for each zone correlating data frequencies and corresponding bit error rates, and a slope of a curve between each two data points is calculated. The slopes are averaged, and the data frequency is calculated based on the average slope. If a difference between the average and default slopes exceeds a first threshold value, or if a spread of the slopes exceeds a second threshold value, the data frequency is calculated based on the average slope and the default slope. In one embodiment, each of the three data points is generated by recording data in the zone at each of three selected data frequencies, reading the recorded data, and calculating bit error rates based on the recorded and read data.

Abstract: Method and apparatus for decoding a one-point algebraic geometric code of dimension k and length n, in order to identify the position of the errors in a received word, the syndromes matrix S, of dimension (n?k)×(n?k) is defined, of which the elements Sij of each line i are calculated, for j between 1 and w(i), where the boundary w is a decreasing function, using the syndrome s of the received word, as well as the matrix S* obtained by “extending” the matrix S, that is to say by calculating the value of certain elements S*ij where j is greater than w(i). This method makes it possible in certain favorable cases to find the erroneous positions of the received word when the number of errors is greater than (n?k+1?g)/2, even if it is not possible to calculate all the elements of S* conventionally required by a two-stage algorithm to perform that correction.