Abstract: The present invention concerns a device having a first and a second differential oscillators (1, 2; 1?2?) coupled to and in quadrature-phase with each other, comprising first and second resonant electronic means (L1, C1, C2; L2, C3, C4) respectively, which are apt to provide, respectively on first two and second two terminals (NODE—1, NODE—2; NODE—3, NODE 4), first two and second two oscillating signals (VNODE—1, VNODE—2; VNODE—3, VNODE—4), said first two oscillating signals (VNODE—1, VNODE—2) being in phase opposition to each other and in quadrature-phase with said second two oscillating signals (VNODE—3, VNODE—4), the device being characterised in that it comprises first generator electronic means (M13-M24) apt to detect first instants of passage through a first reference value of each one of said first oscillating signals (VNODE—1, VNODE—2) and to generate first power supply pulses for said second resonant electronic means (L2, C3, C4) in second instants, and in that it comprises second generator electroni

Abstract: One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.

Abstract: A method for compensating an oscillation frequency, a device, and a phase locked loop (PLL) is applied in the LC oscillating loop, including: sending voltage control signals to one end of a variable capacitor of an LC oscillating loop to generate oscillating signals in the LC oscillating loop through the voltage control signals; obtaining variable bias voltage that reflects changes of external parameters; and sending the variable bias voltage to the other end of the variable capacitor to compensate changes to the oscillation frequency of oscillation signals generated in the LC oscillating loop. This invention compensates the changes to the oscillation frequency of the circuit that contains the LC oscillating loop and improves the stability of the circuit oscillation frequency by sending bias voltage to one end of the variable capacitor of the LC oscillating loop.

Abstract: An atomic oscillator includes: a gas cell in which a gaseous metal atom is sealed; heating units heating the gas cell to a predetermined temperature and being a first heater and a second heater; a light source of exciting light exciting the metal atom in the gas cell; a light detecting unit detecting the exciting light which has passed through the gas cell; a substrate including at least a temperature controlling circuit for the heating units; a first heater wiring coupling the first heater and the substrate; a second heater wiring coupling the second heater and the substrate; and a third heater wiring coupling the first heater and the second heater. In the atomic oscillator, the gas cell includes a cylindrical portion; and windows which respectively seal openings at both ends of the cylindrical portion and constitute an incident surface and an emitting surface on an optical path of the exciting light.

Abstract: A phase locked loop can reduce a locking time, thereby efficiently reducing power in a locking operation. The phase locked loop includes a phase detector, a control voltage generator, a voltage controlled oscillator and a start-up driver. The phase detector detects a phase difference between a reference clock and a feedback clock to generate a detection signal corresponding to the detected phase difference. The control voltage generator generates a control voltage having a voltage level corresponding to the detection signal. The voltage controlled oscillator generates an internal clock having a frequency corresponding to a voltage level of the control voltage. The start-up driver drives a control voltage terminal to a predefined start-up level in response to a start-up level multiplex signal corresponding to a frequency of the reference clock prior to activation of the voltage controlled oscillator.

Abstract: An oven-controlled crystal oscillator includes a circuit board, a crystal unit surface-mounted on the circuit board, and a temperature control circuit that maintains operating temperature of the crystal unit constant. The temperature control circuit includes a heating resistor, a power transistor that supplies power to a heating resistor, and a temperature sensitive resistor that detects temperature of the crystal unit. The heating resistor is formed, as a film resistor, on a surface of the circuit board in an area thereof in which the crystal unit is located. The temperature sensitive resistor is provided on the circuit board as a film resistor.

Abstract: An oscillator unit is configured such that a frequency adjustment unit of a synthesizer used by a controller is smaller than a frequency variation tracking capability of a demodulator connected to an output side of a frequency converter. This structure successfully combines the temperature compensation control of an oscillator unit and the receiving process of a high-frequency receiving device. Accordingly, an oscillator unit with large temperature coefficient is applicable to high-frequency receiving devices.

Abstract: Circuits and methods for generating an oscillator output. The circuit generally includes a ring oscillator, with a series of inverters connected in series and an LC resonator tank (or a variable resistance) coupled to the input and output of the inverter series. The method generally includes the steps of applying an operating voltage to such a circuit and generating an oscillator signal. The circuits and methods may be employed as a VCO component of a phase-locked loop. The upper limit of the oscillator signal frequency may be configured by altering or controlling the variable resistance and/or one or more parameters of the LC resonator tank. The circuit design demonstrates a high tolerance to variations in circuit or circuit component values.

Abstract: An apparatus for generating an output signal having a particular frequency includes an oscillator, a first tuning module, and a second tuning module. The oscillator generates an output signal associated with an output frequency. When coupled to the oscillator, the first tuning module is capable of inducing, within a first amount of time, a change in the output frequency of a particular magnitude. When coupled to the oscillator, the second tuning module is capable of inducing, within a second amount of time, a change in the output frequency of the same magnitude. The second amount of time is greater than the first amount of time. The selector couples a selected one of the first tuning module and the second tuning module to the oscillator based on a difference between a frequency-divided version of the output signal and a reference signal.

Abstract: A lock-aid circuit and method is applied to a phase lock loop (PLL) having a voltage controlled oscillator (VCO), wherein the lock aid is coupled with the input of the VCO. In one example, the lock aid includes a Schmitt trigger having an output, a switch having an output and an input coupled to the output of the Schmitt trigger, and a voltage controlled current source coupled with the output of the switch.

Abstract: Embodiments of the present invention include an integrated circuit comprising an integrated transmission line, wherein the integrated transmission line is used as a timing reference for a feedback loop and wherein the feedback loop and the transmission line are integrated on a single integrated circuit. The feedback loop and transmission line may be used as a frequency generator or controlled delay, for example. In another embodiment, the present invention includes a timing loop with first and second commutating phase detectors.

Abstract: A signal generating circuit includes a relaxation oscillator operating to alternately generate a first ramp signal that is periodic at a frequency of the relaxation oscillator and a second ramp signal that is periodic at the frequency of the relaxation oscillator and is out of phase with respect to the first ramp signal The first ramp signal is compared to a first reference voltage and the state of a first flip-flop is changed if the first ramp signal exceeds the first reference voltage. The second ramp signal is compared to the first reference voltage and the state of a second flip-flop is changed if the second ramp signal exceeds the first reference voltage. The first flip-flop is reset in response to a first level of the first ramp signal and the second flip-flop is reset in response to a second level of the second ramp signal.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present inventions relate to oscillator systems which employ a plurality of microelectromechanical resonating structures, and methods to control and/or operate same. The oscillator systems are configured to provide and/or generate one or more output signals having a predetermined frequency over temperature, for example, (1) an output signal having a substantially stable frequency over a given/predetermined range of operating temperatures, (2) an output signal having a frequency that is dependent on the operating temperature from which the operating temperature may be determined (for example, an estimated operating temperature based on a empirical data and/or a mathematical relationship), and/or (3) an output signal that is relatively stable over a range of temperatures (for example, a predetermined operating temperature range) and is “shaped” to have a desired turn-over frequency.

Abstract: There are many inventions described and illustrated herein.

Abstract: A fractional-N frequency synthesizer supporting multi-band operation, having variable frequency resolution obtained by sigma-delta modulating a multi-bit frequency resolution control signal having at least one pulse, the at least one pulse having a period of P and a variable duty cycle. Frequency resolution can be increased by changing the duty cycle and without increasing input bits to the sigma-delta modulator. Thus, a core size of the sigma-delta modulator may be reduced.

Abstract: A single chip digital frequency synthesiser (1) for synthesising a frequency swept synthesised output signal of a selectable frequency sweep comprises a direct digital synthesiser (5) which produces the frequency swept synthesised output signal on an output terminal (7) in response to values of a frequency control digital word applied to a frequency control input (8) thereof by an on-chip data processing circuit (25). An on-chip programmable data storing circuit (12) is programmable to store data indicative of a selected mode in which the digital frequency synthesiser (1) is to operate, and to store data indicative of selectable frequency and the time domains of the frequency swept synthesised output signal to be produced.

Abstract: A voltage controlled current source outputs oscillator drive current and oscillator equivalent current. A signal oscillator outputs first source oscillation signal and second source oscillation signal. A differential amplifier outputs first amplification oscillation signal and second amplification oscillation signal. First switch circuit and second switch circuit output first current oscillation signal and second current oscillation signal, respectively. A first current value converter-amplifier circuit converts a value of the first current oscillation signal whereas a second current value converter-amplifier circuit converts a value of the second current oscillation signal, so that the thus converted values become output current finally. An adder outputs to the differential amplifier a differential amplifier drive current in which equivalent current for use with conversion is added up with the oscillator equivalent current outputted from the voltage controlled current source.

Abstract: An integrated circuit has an internal oscillator circuit for being connected to an external frequency source such as a crystal or a ceramic resonator. The internal oscillator circuit has an inverting amplifier across the frequency source terminals to establish an oscillation there. One terminal of the frequency source is coupled to one input of the comparator and to a second input of the comparator through a low pass filter. Coupling the output of the low pass filter to the second input of the comparator is for preventing a DC offset from developing between the two inputs of the comparator. The other terminal of the frequency source is coupled to the second input of the comparator through a high pass filter. The high pass filter provides the comparator with a larger voltage differential to increase noise margin. Noise margin is further improved by allowing an increase in hysteresis in the comparator.

Abstract: Circuits, systems, and methods for fine tuning crystal frequency accuracy are disclosed. One such circuit fine tunes crystal frequency accuracy with a tunable fractional capacitance. The circuit includes an effectively constant capacitance coupled, e.g., fixedly, with the crystal. A second capacitance is controllably coupleable with the crystal. A switching device is controllable for switchably coupling the second capacitance with the crystal. An effective capacitance value associated with the second capacitance varies according to a time associated with that switchable coupling. The crystal resonating frequency changes according to a capacitive loading thereof, which includes the first capacitance and the effective capacitance value of the second capacitance, effectively time multiplexed therewith.

Abstract: A method, algorithm, software, architecture, circuit, and/or system for detecting an idle condition and maintaining a frequency of a clock/data recovery circuit are disclosed. In one embodiment, a method of maintaining a frequency of a clock/data recovery circuit can include the steps of: (i) comparing a difference value from a differential signal with a predetermined threshold (or value); (ii) controlling a variable frequency oscillator (VFO) with a frequency detector when the difference value is less than the threshold for at least a predetermined integration time; and (iii) controlling the VFO with a phase detector receiving the differential signal when the difference value is greater than the threshold. Embodiments of the present invention can advantageously provide a reliable and simplified design approach for clock data recovery (CDR) circuits operable with low power mode transmitters.