Abstract: An integrated circuit (IC) with an oscillator and electrostatic discharge (ESD) protection in which the parasitic capacitance of the ESD protection circuitry is disassociated from the oscillator circuitry to minimize loading of the tank circuit thereby minimizing degradation of the tank circuit quality factor (Q).

Abstract: A voltage controlled oscillator that can rapidly change frequencies over a wide range is disclosed. The voltage controlled oscillator has a transistor having a base, an emitter and a collector. An output port and a power supply port are connected to the collector. A high pass filter is connected between ground and the base of the transistor. A tuning element is connected between the high pass filter and ground. The tuning element includes a pair of varactor diodes. The varactor diodes have their cathodes connected together at a first node. A series combination of a resistor and inductor are connected between a tuning port and the first node. A capacitor is connected between the first node and the emitter.

Abstract: According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.

Abstract: Quadrature demodulator and quadrature modulator which comprise a first oscillator and a second oscillator, a separate excitation signal being fed to the first and second oscillator to determine the time at which switching between two stable states takes place, and the quadrature demodulator and quadrature modulator further comprise excitation elements In the quadrature demodulator, an input signal is fed, which influences a parameter of one of the elements of the first and the second oscillator and produces a set of quadrature output signals. In the quadrature modulator, a first and second quadrature signals are fed to the quadrature modulator, which influences a parameter of one of the elements of the first and the second oscillator, and the quadrature modulator further comprises summing elements to produce a modulated output signal.

Abstract: A frequency-divided reference frequency clock is provided as a reference input to a phase comparator. An oscillation frequency signal of a controllable oscillator, having a frequency associated with another reference frequency clock, is frequency divided by a frequency division factor switching type comparison-input frequency division circuit. The resultant frequency-divided clock is provided as a comparison input to the phase comparator. The frequency division factor of the comparison-input frequency division circuit is switched from one to another based on a frequency division factor control signal to generate an oscillation frequency signal having a predetermined frequency ratio relative to another reference frequency clock. Thus, three reference frequency clocks of 27 MHz, 33.8688 MHz, and 36.864 MHz in accord with the MPEG format are obtained with a sufficient S/N ratio.

Abstract: The present invention relates to a crystal oscillator circuit in which the output level is maintained to prevent changes in oscillation frequency due to variations in power voltage. This crystal oscillator circuit comprises a resonance circuit formed of a crystal oscillator (which acts as an inductor component) and dividing capacitors, an oscillation amplifier formed of ECL circuitry driven by a power voltage connected to the resonance circuit, and a pull-down resistor between an output terminal of the ECL circuit and ground. The pull-down resistor acts as serially-connected dividing resistors and also a bias capacitor is provided between a connection point between those dividing resistors and ground. The present invention also relates to a frequency-switching oscillator having a simple circuit design and a small number of components.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: A control voltage window generator that tracks process, voltage supply, and temperature variations for a voltage controlled oscillator includes: a first transistor of a first conductivity type coupled between a supply voltage node and an upper control voltage node; and a second transistor of a second conductivity type coupled to the upper control voltage node to compensate for process variations in devices of the first conductivity type. Additionally, a target pull-in voltage generator includes circuitry for providing a pull-in control voltage that will always be inside the control voltage window, and also tracks process, voltage supply, and temperature variations.

Abstract: A CMOS Pierce crystal oscillator. A clock generator with activation control, for generating a clock signal. The clock generator comprises an amplifier, a shaping circuit and a diagnostic circuit. The amplifier is capable of being coupled to an external oscillation source through an input pad and an output pad to generate an oscillating signal, the shaping circuit is capable of being coupled to the output pad, for shaping the oscillating signal to generate a clock signal, and the diagnostic circuit is capable of being coupled to the output pad, for asserting a ready signal when amplitude of the oscillating signal exceeds a predetermined portion of a full swing voltage.

Abstract: A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.

Abstract: An oscillator circuit and an oscillation stabilizing method are provided that can improve the productivity of products, stabilize an oscillating operation, and achieve more stable operations for a system supplied with oscillation output. An output from a variable capability oscillator circuit is received by two inverters having different threshold values. Regarding voltage values that are exceeded when oscillation is stabilized in the inverters, the boundaries of the voltage values are set as an astable boundary and an astable boundary which are the threshold values of the inverters, outputs from the inverters are counted by a stable oscillation period shortening circuit based on the timing of a clock used for the system, and the capability of the variable capability oscillator circuit is maximized until oscillation is stabilized, thereby further shortening a stable oscillation period.

Abstract: A quartz-crystal oscillator circuit substantially reduces the start-up time of the crystal oscillator circuit by utilizing a start-up time reduction circuit that adds additional gain to the crystal oscillator circuit during the start-up period, and removes the additional gain as the oscillator circuit nears steady state operation. Furthermore, the start-up time reduction circuit dynamically monitors the oscillation amplitude. If the build up of oscillation is interrupted, the additional gain will be re-applied.

Abstract: A PWM signal generator and generating method for generating one or two pulses having a pulse width or a total pulse width corresponding to a value represented by a pulse code modulation digital signal and placed in a symmetric positional relationship with respect to the position of one half of a predetermined length. A first pulse and a second pulse are generated in accordance with a value represented by the digital signal. The difference in pulse width between the first and second pulses is output as a first pulse width modulation signal. When the value represented by the digital signal is zero, the first pulse and second pulse are equal in pulse width. When the value represented by the digital signal changes by one, one of the first and second pulses does not change in pulse width, while the other of the first and second pulse changes in pulse width by two slots.

Abstract: The problem of interference and coupling between circuits that arises in reducing the size of a voltage-controlled oscillator by using low temperature co-fired ceramics (LTCC) substrate technology is alleviated. A voltage-controlled oscillator includes an amplifier a surface acoustic wave device 15 that forms a feedback circuit for the amplifier; a frequency adjuster that is provided the feedback circuit and has a filter configuration; a phase shifter 13 including a hybrid coupler having an additional controller that receives a control voltage from an external source and changes a phase in an oscillation loop; an equal power distributor 12 that equally distributes output power in the oscillation loop and outputs the power to the outside of the oscillation loop; and a delay line 16 concentratedly provided a place where coupling or interference does not occur the oscillation loop for correcting a phase condition in the oscillation loop.