Abstract: A tunable ring oscillator, in accordance with the teachings described herein, may include one or more delay circuits having a coarse tuning circuitry and a fine tuning circuitry. The coarse tuning circuitry may be used to set one of a minimum time delay or a maximum time delay as a function of a coarse tuning input. The fine tuning circuitry may be used to adjust between the minimum time delay and the maximum time delay as a function of a fine tuning input.

Abstract: Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.

Abstract: An amplitude-controlled oscillator circuit includes an oscillator for providing a frequency signal having a controllable signal amplitude, a divider circuit for a frequency division of the frequency signal, a minimum amplitude of the frequency signal being associated to the divider circuit and the divider circuit being formed to output a divided frequency signal having a predetermined quality when the signal amplitude is greater than or equal to the minimum amplitude. In addition, the amplitude-controlled oscillator circuit includes a controller for controlling the signal amplitude of the frequency signal, the controller being formed to control the signal amplitude such that it is greater than or equal to the minimum amplitude. It is possible by means of such an amplitude-controlled oscillator circuit to ensure in a simple and low-cost manner that the divided frequency signal has a predetermined quality for example within a wide temperature range.

Abstract: An oscillator circuit may include a latch circuit, a feed-back circuit, and an input circuit. The latch circuit may be configured to generate an oscillating output signal responsive to first and second input signals, and the feed-back circuit may be configured to generate first and second complementary feed-back signals responsive to the oscillating output signal from the latch circuit. The input circuit may be configured to generate the first and second input signals responsive to the first and second complementary feed-back signals. Related methods are also discussed.

Abstract: Circuit for generating a spread spectrum clock (CGSSC) that employs a mechanism to modulate the input voltage (V_ctrl) to the VCO to achieve dithering. The CGSSC includes a voltage controller oscillator (VCO) that generates an output signal (F_out). The VCO includes an input coupled to a voltage control node for receiving a voltage signal and an output for generating a clock signal that has a frequency dependent on the received voltage signal. A VCO input voltage modulation mechanism (VIVMM) is coupled to the voltage control node (V_ctrl) for modulating or adjusting the voltage at the VCO input voltage node in a controlled manner to generate a spread spectrum clock.

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

Abstract: A CMOS single-ended frequency doubler with improved subharmonic rejection and low phase noise which allows a single ended reference signal to be utilized in a Balanced Colpitts oscillator. The input is reproduced with a 180-degree phase shift for the opposite Colpitts transistor. This is achieved by adding two PMOS transistors. One transistor is placed as a follower, which reproduces any voltage shift applied to its gate to its source. Another transistor is a matching transistor for balance. By applying the single-ended signal to the gate of the follower transistor, it is reproduced at the source. The rest of the circuit takes advantage of the summing of two period currents with a 180-degree phase shift. The present invention achieves superior performance for frequency doubling due to the squaring of the gate voltage in the corresponding drain current. As a result, the double frequency component is further enhanced.

Abstract: A low noise charge pump for use in a PLL-based frequency synthesizer. The charge pump includes a timing controller and a plurality of charge-pump circuits. The timing controller receives a reference signal to generate a plurality of enable signals having non-overlapping phases, where the frequency of each enable signal is equal to that of the reference signal divided by the number of the enable signals. The charge-pump circuits are coupled in parallel and operate in a time-interleaved manner according to the enable signals. In response to a first and second control signal, the charge-pump circuits are able to generate respective output currents which are multiplexed together to form a charge-pump current.

Abstract: A wireless communication unit (100) comprises a voltage controlled oscillator (123) having an active device (450) operably coupled to a first variable capacitance (425) to provide a variable capacitance value based on an applied steering line voltage, and a feedback network comprising a resonator (475), operably coupled to an output of the active device, for feeding power back to an input of the active device to sustain oscillations (123). Notably, a second variable capacitance is operably coupled to receive a control voltage from the steering line (405) and located between the resonator (475) and the active device (450).

Abstract: Disclosed is a quadrature VCO (voltage controlled oscillator) which comprises a first delay cell including a first switching transistor and a second switching transistor, the first delay cell outputting first and second in-phase signals with different phases; and a second delay cell including a third switching transistor and a fourth switching transistor, the second delay cell outputting first and second quadrature-phase signals with different phases. The first and second quadrature-phase signals are applied to back gates of the first and second switching transistors, and the first and second in-phase signals are applied to back gates of the fourth and third switching transistors.

Abstract: The present invention relates to a static magnetic field applying structure for use in an atomic oscillator in which plural sets of magnetic field generating means are provided with spacing interposed among them, and a resonance cell is disposed in a space between the magnetic field generating means. The object of the present invention is to realize the static magnetic field applying structure which can be small-sized and produced at a low cost.

Abstract: An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

Abstract: Disclosed is a gate pulse modulator. The inventive gate pulse modulator includes an input control unit receiving inputs from a gate high signal terminal, a clock signal terminal and a control signal terminal. In addition, the inventive gate pulse modulator includes an output control unit connected to the gate high signal terminal, the control signal terminal and an external driving signal terminal, wherein the output control unit supplies a base voltage to a gate driving unit when the control signal is low, and in the state where the control signal is high, the output control unit supplies a gate high voltage to the gate driving unit if the clock signal is high and supplies a driving voltage to the gate driving unit if the clock signal is low. In addition, the invention further comprises a time delay unit connected to a stage prior to the input control unit, so that the gate high voltage delayed for a predetermined length of time is supplied to the gate driving unit.

Abstract: A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging/discharging thereafter, and vice versa. The present invention makes use of the turbo-charging/discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.

Abstract: The oscillator circuit comprises a capacitor and first to fourth constant current supplies and switches are connected to the capacitor. Both terminals of the capacitor are used for charges and discharges. One period comprises four steps; charging the first terminal of the capacitor, discharging the second terminal, charging the first terminal, and discharging the second terminal.

Abstract: A method, an apparatus, and a computer program are provided to minimize filter capacitor leakage in a Phased Locked Loop (PLL). In high frequency processors and devices, filter leakage currents can cause substantial problems by causing PLLs to drift out of phase lock. To combat the leakage currents, a dummy filter and other components are employed to provide additional charge or voltage to a low pass filter during lock. The provision of the charge or voltage exponentially decreases the rate of decay of voltage across the low pass filter caused by leakage currents.

Abstract: The control voltage for a VCO (voltage controlled oscillator) is produced in a phase locked loop which in turn is controlled by a computer (40) including an integrated analog circuit (42). First the oscillator control voltage is set to a predetermined value. Then, voltage varying steps are performed. For performing these steps, the circuit includes a main frequency divider and a reference frequency divider both functioning as counters. The beginnings of the counting of each divider are synchronized with each other. The oscillator control voltage is increased by a predetermined voltage difference or increment when the reference divider completes its counting period prior to the main divider completing its counting. The oscillator control voltage is decreased by a predetermined voltage difference or decrement when the main divider finishes its counting period prior to the reference divider finishing its count.

Abstract: An oscillator circuit is provided that is preferably a crystal oscillator, where voltage placed across the crystal is regulated. The regulated voltage or amplitude of the cyclical signal across the crystal is monitored and maintained through a regulation circuit that measures a peak voltage across the crystal. Once the peak voltage exceeds a predetermined setpoint value, then a controller within the regulation circuit will reduce a biasing current through an amplifying transistor within the amplifier coupled across the crystal input and output nodes. By regulating the biasing current, gain from the amplifier is also regulated so that unwanted non-linearities and harmonic distortion is not induced within the crystal to cause frequency distortion and unwanted modes of oscillation within the crystal. The amplifier is preferably symmetrical in that the amplifier sources and sinks equal current to reduce unwanted peaks at the negative or positive half cycles of the sinusoidal signal.

Abstract: An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

Abstract: A crystal oscillator comprises a rectangular circuit substrate for mounting circuit devices and its metal cover, said circuit substrate has grooves on each long side and on each short side and said metal cover has projections at each aperture end corresponding to the grooves, and which has a swelling from external to internal in each of the projections, wherein both the grooves provided on each short side and the projection of said metal cover are provided at one end of each long side or each short side.