Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: A variable capacitance circuit capable of switching on and off a variable capacitance function, includes variable capacitance means formed such that variable capacitance elements whose capacitance values change according to a voltage value of a supplied capacitance control voltage are connected so as to be paired and a plurality pairs of variable capacitance elements are connected in parallel forming multiple stages; bias voltage generation means for generating bias voltages of different voltage values based on a constant voltage from a constant voltage source; and an on-off switch for the variable capacitance function, in which the variable capacitance function of the variable capacitance means is turned on by supplying the bias voltage to the variable capacitance element of each stage of the variable capacitance means and turned off by grounding the bias voltage of each voltage value.

Abstract: Embodiments of the present invention reduce static phase offset in timing loops. In one embodiment, the present invention includes a timing loop comprising first and second phase detectors, wherein during a first time period, the first phase detector is coupled in a closed timing loop and the second phase detector is decoupled from the closed timing loop and calibrated, and during a second time period, the second phase detector is coupled in a closed timing loop and the first phase detector is decoupled from the closed timing loop and calibrated.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=1/4*(f4) causing a coarse frequency adjustment and a signal A=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: An example embodiment is directed to shifting the common mode voltage of an analog oscillation stage toward a center line between the upper and lower power-supply rails of a first digital circuit. The first digital circuit has a digital input port adapted to respond to signal transitions defined between the supply rails, and the analog oscillation stage generates an oscillating analog signal that has a common-mode voltage that is not centered between the upper and lower power-supply rails. The oscillating analog signal, which drives the digital input port, changes alternately with the phases of the oscillating analog signal. To shift the common mode voltage of an analog oscillation stage toward the center line between the rails, a feedback circuit generates a contending digital signal that drives the digital input port with alternating states as defined by opposite phases.

Abstract: The present invention is based on the objective of constructing a PLL as arbitrary frequency generator for frequency multiplication purposes without utilizing a VCO. The invention shows a solution which can be realized with a pure digital circuit which can be easily integrated on a chip. In digital oscillators, the frequency can be changed, by changing over the number of time-delay elements. It is also possible to realize very slight frequency changes per switching stage by changing over between different elements with very similar delay times. In addition, a pulse-width modulator is utilized that periodically changes over between two or more of these stages and consequently different frequencies. Furthermore a PLL is introduced using such a frequency generator.

Abstract: An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter coupled to the digital PFD for sampling the detection signal according to an oscillator signal to thereby generate a count value; a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value; a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal; and a frequency divider coupled to the DCO and the digital PFD for generating the feedback signal by dividing the oscillator signal.

Abstract: A variable capacitance circuit includes a first and a second capacitor. A switch having an associated first nonlinear capacitance, selectively couples the first and second capacitors. To compensate for the first nonlinear capacitance, a second nonlinear capacitance is coupled to the switch that has a capacitance value responsive to a change in voltage that moves in a direction of change opposite to a direction of change of the first nonlinear capacitance.

Abstract: In a function generating circuit which comprises a temperature sensor 1 for outputting an output current (Ilin) with a linear temperature characteristic or an output voltage (Vlin) with the linear temperature characteristic, a cubic function generating circuit 2 for receiving the output current (Ilin) or the output voltage (Vlin) of the temperature sensor 1 as an input and generating a cubic temperature characteristic voltage (Vcub), and a control data storing circuit 3 for recording control data to control the output characteristic of the cubic function generating circuit 2, an external control signal is applied to the temperature sensor 1 from an external control terminal 4 to cause the sensor to output variably the output current (Ilin) or the output voltage (Vlin) such that the temperature characteristic of the cubic function generating circuit 2 can be controlled at the ordinary temperature.

Abstract: Method and apparatus for calibration of a low frequency oscillator in a processor based system. A method for calibrating an on-chip non-precision oscillator. An on-chip precision oscillator is provided having a known frequency of operation that is within an acceptable operating tolerance. The on-chip precision oscillator is used as a time base and then the period of the on-chip oscillator is measured as a function of the time base. The difference between the measured frequency of the on-chip non-precision oscillator and a desired operating frequency of the on-chip non-precision oscillator is then determined. After the difference is determined, the frequency of the on-chip non-precision oscillator is adjusted to minimize the determined difference.

Abstract: A temperature correcting apparatus divides an actually measured waveform of correcting voltages, which are required at each of different temperatures, by a minimum resolution of D/A conversion; obtains voltage digital values representing voltage values at individual dividing points of the actually measured waveform, and obtains times corresponding to the voltage digital values; prestores pairs of the voltage digital values and times together with addresses as correcting data; reads out the correcting data in response to the detection address representing the temperature; extracts or calculates from the correcting data the voltage digital values and times about the correcting voltages required by the detection address; and sequentially supplying a D/A converter with the resultant voltage digital values in synchronization with the corresponding times.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: An R-C oscillator (200) is configured to vary the two voltage levels that are used to control the oscillation, such that the variation in oscillation frequency with temperature is minimized. A first resistor (R1) is used to control one of the voltage levels, and a second resistor (R2) having a temperature coefficient that differs from the temperature coefficient of the first transistor is used to control the other voltage level. The first resistor (R1) also controls the current used to charge and discharge the capacitor (C) used to effect the oscillation. By the appropriate choice of resistance values, the variations of the control voltages and current are such that the time to charge and discharge the capacitor (C) between the control voltages remains substantially constant with temperature. Preferably the resistance values are selected to also compensate for temperature variations in the delay of the feedback loop.

Abstract: An oscillator includes a resonant circuit of at least one inductance device and at least one tunable capacitance. The tunable capacitance is implemented through diffusion capacitances of at least one current-carrying transistor. The tunable capacitance has a first differential amplifier having a first transistor and a second transistor and a second differential amplifier having a third transistor and a fourth transistor Electrical properties of the first transistor and second transistor are complementary to electrical properties of the third transistor and fourth transistor, and control connections of the first transistor and the third transistor are connected to one another. Control connections of the second transistor and the fourth transistor are connected to one another. Second current connections of the first transistor and the third transistor are connected to one another, and second current connections of the second transistor and the fourth transistor are connected to one another.

Abstract: A quadrature VCO comprises: a first delay cell including a first differential VCO coupled between a power supply and a first current source; and first and second coupling transistors that each include a first terminal, a second terminal coupled to the power supply, and a third terminal, and that vary a current flowing from the second terminal to the third terminal according to quadrature-phase signals applied to the first terminal; and a second delay cell including a second differential VCO coupled between a power supply and a second current source; and third and fourth coupling transistors that each include a first terminal, a second terminal coupled to the power, and a third terminal, and that vary a current flowing from the second terminal to the third terminal according to in-phase signals applied to the first terminal.

Abstract: Certain spatio-temporal symmetries induce one array of a two-array coupled network of oscillators to oscillate at N times the frequency of the other array, where N is the number of oscillators in each array.

Abstract: A local oscillator circuit has a control loop that locks the oscillation of a voltage-controlled oscillator at a programmable frequency. The control loop includes a voltage generator that generates a control voltage for the voltage-controlled oscillator, and a current generator that generates a current to raise and lower the control voltage. The magnitude of the current is switched according to the programmed frequency. The magnitude of the current can thereby be adjusted so that the local oscillator circuit achieves lock within a predetermined time, without the need for analog comparison of the control voltage.

Abstract: Charge current in a charge pump of a phase locked loop is equalized by controlling one of the direct current sources with a feedback signal derived from the common mode voltage of a fully differential phase locked loop filter.

Abstract: In the present invention, a temperature compensation circuit is provided. The temperature compensation circuit includes a first oscillator for providing a first clock signal, a timer electrically connected to the first oscillator for clocking a specific time period, a voltage regulator for generating a constant voltage, a second oscillator electrically connected to the voltage regulator for providing a second clock signal, and a counter electrically connected to the second oscillator for counting within the specific time period based on the second clock signal so as to obtain a counting value, and thereby a frequency of the second oscillator is obtained for the temperature compensation.

Abstract: A hybrid frequency synthesizer includes an analog phase lock loop (PLL), a digital PLL, and a control circuit to control an output oscillator. The control circuit assigns control of the output oscillator between the analog PLL and/or the digital PLL depending on a state of lock of the analog PLL and/or the digital PLL. During a frequency acquisition mode, the digital PLL provides a coarse control of the output oscillator. During a phase capture mode, the analog PLL provides a fine control and the digital PLL provides a coarse control of the output oscillator. During the phase capture mode, the analog PLL control signal and the digital PLL control signal may be given a percentage of control over the output oscillator depending on the state of lock of the analog PLL and/or the digital PLL. During a phase lock mode, the analog PLL controls the output oscillator.