Patents Examined by Jeffrey T Carley
  • Patent number: 11888279
    Abstract: PROBLEM TO BE SOLVED: To provide a laser jointing method that joints two materials while imparting a sufficient strength thereto and minimizing heat influence. SOLUTION: The method overlaps first and second materials (V1, V2) on each other and irradiates the surface of the first material (V1) with a laser light (103) from the side of the first material (V1). When jointing both materials (V1, V2), the method intermittently irradiating an overlapped part of the first and second materials (V1, V2) with the laser light while moving the laser light (103) to form a welding bead (1) on the surface of the first material (V1), wherein the length of the welding bead (1) is formed gradually shorter.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: January 30, 2024
    Assignee: TE Connectivity Germany GmbH
    Inventors: Andre Martin Dressel, Gunther Chritz, Jens Huber
  • Patent number: 11883011
    Abstract: The present invention presents a method of fabrication for a physiological sensor with electronic, electrochemical, and chemical components. The fabrication method comprises steps for manufacturing an apparatus comprising at least one electrochemical sensor, a microcontroller, and a transceiver. The fabrication process includes the steps of substrate fabrication, circuit fabrication, pick and place, reflow soldering, electrode fabrication, membrane fabrication, sealing and curing, layer bonding, and dressing. The physiological sensor is operable to analyze biological fluids such as sweat.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: January 30, 2024
    Assignee: CORESYTE, INC.
    Inventors: Adam Pizer, Dalton Pont, John V. Chiochetti
  • Patent number: 11875949
    Abstract: A method of manufacturing an electronic component includes preparing an unfired multilayer body including first and second main surfaces facing each other in a stacking direction, first and second side surfaces facing each other in a width direction, and first and second end surfaces facing each other in a length direction, bonding one main surface of the unfired multilayer body to an elongated first adhesive sheet, conveying the first adhesive sheet in a first direction in which the first adhesive sheet approaches an elongated second adhesive sheet, and bonding one side surface of the unfired multilayer body to the second adhesive sheet, conveying the second adhesive sheet in a second direction different from the first direction to peel off the unfired multilayer body from the first adhesive sheet, polishing another side surface of the unfired multilayer body, and forming a first insulating layer on the polished another side surface.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 16, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Daiki Fukunaga
  • Patent number: 11871671
    Abstract: A bonded body includes a supporting substrate, a silicon oxide layer provided on the supporting substrate, and a piezoelectric material substrate provided on the silicon oxide layer and composed of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalate. The surface resistivity of the piezoelectric material substrate on the side of the silicon oxide layer is 1.7×101 5?/? or higher.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 9, 2024
    Assignee: NGK INSULATORS, LTD.
    Inventors: Yuji Hori, Takahiro Yamadera, Tatsuro Takagaki
  • Patent number: 11854742
    Abstract: A capacitor integrated structure, a capacitor unit and a manufacturing process thereof are provided. The manufacturing process of capacitor units includes the steps of: forming a plurality of capacitor stacking structures on a substrate having an insulation layer thereon; performing a first cut on insulation dividers provided between the adjacent capacitor stacking structures to form a plurality of recesses that expose first conductive portion and second conductive portion of each of the capacitor stacking structures; filling a metallic material in the recesses to form a plurality of metallic dividers that are electrically connected to the first conductive portion and the second conductive portion of each of the capacitor stacking structures; performing a second cut on the metallic dividers to form a plurality of independent capacitor units; and forming metallic walls on two opposite sides of each of the capacitor units, so as to provide a capacitor unit having two end electrodes.
    Type: Grant
    Filed: June 19, 2021
    Date of Patent: December 26, 2023
    Assignee: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventors: Wei-Yu Lin, Kuo-Yu Yeh
  • Patent number: 11856707
    Abstract: An automatic backup pin arrangement operation includes a backup plate facing a lower surface of circuit board where backup pins stored in a stock areas are picked up with an XY-robot to be automatically arranged at positions of the backup plate designated in a production job. In a case where there is no free space in the stock areas for an unnecessary backup pin removed from the backup plate to be placed when a production job for changing the arrangement of the backup pins is switched, at least a part of a region of the backup plate facing a lower surface of the circuit board, which does not interfere with a mounted component on a lower surface side of the circuit board, is used as retraction area, and the unnecessary backup pin that cannot be retracted to the stock area is retracted to the retraction area.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 26, 2023
    Assignee: FUJI CORPORATION
    Inventors: Hideya Kuroda, Hiroyoshi Sugita
  • Patent number: 11844279
    Abstract: An apparatus for fabricating a piezoelectric transducer includes a base and a piezoelectric powder depositor to traverse the base and deposit a plurality of layers of piezoelectric powder on the base. The apparatus also includes an electrode disposed at an end of a boom of which is moveable to a selected location with respect to the base and a voltage source to apply a voltage to the electrode to establish an electric field between the electrode and base with sufficient strength to sinter and pole each layer of piezoelectric material and a controller having instructions to deposit the plurality of layers of the piezoelectric powder on the base and to control a position of the electrode and actuate the voltage source to the electrode to sinter and pole the layer of piezoelectric material at defined locations after each layer is deposited to form the piezoelectric transducer in a selected shape.
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: December 12, 2023
    Assignee: BAKER HUGHES OILFIELD OPERATIONS LLC
    Inventors: Elan Yogeswaren, Navin Sakthivel, Otto Fanini
  • Patent number: 11832520
    Abstract: In some embodiments, the present disclosure relates to a processing tool that includes a wafer chuck disposed within a hot plate chamber and having an upper surface configured to hold a semiconductor wafer. A heating element is disposed within the wafer chuck and configured to increase a temperature of the wafer chuck. A motor is coupled to the wafer chuck and configured to rotate the wafer chuck around an axis of rotation extending through the upper surface of the wafer chuck. The processing tool further includes control circuitry coupled to the motor and configured to operate the motor to rotate the wafer chuck while the temperature of the wafer chuck is increased to form a piezoelectric layer from a sol-gel solution layer on the semiconductor wafer.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Chiao-Chun Hsu, Chung-Yi Yu
  • Patent number: 11824511
    Abstract: Methods for depositing bulk layer crystalline material having a predetermined c-axis tilt on a substrate include a first step of depositing a first portion of bulk layer material at a first incidence angle to achieve a predetermined c-axis tilt, and a second step of depositing a second portion of the bulk material layer onto the first portion at a second incidence angle that is smaller than the first incidence angle. The second portion has a second c-axis tilt that substantially aligns with the first c-axis tilt.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 21, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Derya Deniz, Robert Kraft, John Belsick
  • Patent number: 11818847
    Abstract: A resist layer forming method includes a process of laminating a resist layer on a base at a first pressure using a laminate roller having a first temperature, and a process of pressing the resist layer against the base at a second pressure higher than the first pressure using a metal plate having a second temperature lower than the first temperature.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: November 14, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yoshihisa Kanbe, Toyoaki Sakai
  • Patent number: 11806191
    Abstract: A grid of phased array transducers includes a piezoelectric layer and a plurality of ground contact traces. The piezoelectric layer includes a first side and a second side. The plurality of ground contact traces is disposed on the first side of the piezoelectric layer along an elevational direction, where each ground contact trace of the plurality of ground contact traces extends along an azimuthal direction. Further, each phased array transducer of the grid of phased array transducers is disposed between an adjacently disposed pair of ground contact traces of the plurality of ground contact traces. Moreover, each phased array transducer includes at least a portion of at least one ground contact trace of a corresponding pair of ground contact traces, and where each phased array transducer includes a plurality of transducer elements.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 7, 2023
    Assignee: General Electric Company
    Inventors: Douglas Glenn Wildes, Lowell Scott Smith, Kwok Pong Chan, Vadim Bromberg, David Martin Mills, Warren Lee, Timothy James Fiorillo, Chi Tat Chiu
  • Patent number: 11806752
    Abstract: Methods and systems are provided for a single element ultrasound transducer. In one embodiment, a method for the transducer comprises laminating a comb structure and a conductive base package into an acoustic stack with a non-conductive glue, grinding the acoustic stack, and dicing the ground acoustic stack along a plane extending from the top surface of the second fin of the conductive base package to the bottom surface of the acoustic stack. The resulting transducer may have a flat front face with a non-conductive groove separating a ground pad formed by the conductive base package from a signal pad formed by a matching layer of the comb structure.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: November 7, 2023
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Flavien Daloz, Philippe Menage, Edouard Da Cruz, Jean Pierre Malacrida, Giandonato Stallone, Coraly Cuminatto
  • Patent number: 11810703
    Abstract: A multilayer substrate includes an element assembly including a second insulating layer and a first insulating layer arranged in this order from a first side to a second side with respect to a layer stacking direction, a first conductor layer on the first side of the first insulating layer and including a plated layer, and a second conductor layer on the first side of the second insulating layer. The first conductor layer includes a first connection portion and a first circuit portion, and the second conductor layer includes a second connection portion and a second circuit portion. When viewed from the layer stacking direction, the first circuit portion includes an overlapping portion which overlaps the second circuit portion. A portion of the first connection portion connected to the second connection portion has a maximum thickness greater than a maximum thickness of the overlapping portion.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yuki Ito
  • Patent number: 11805597
    Abstract: A high-throughput method of manufacturing a liquid metal circuit may include applying a liquid metal to an alloying metal pattern on an elastic substrate to form the liquid metal circuit. The elastic substrate may have a surface area greater than 1 square inch. The liquid metal circuit may include a plurality of liquid metal circuits on the elastic substrate. Methods of using the liquid metal circuit are also described.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: October 31, 2023
    Assignee: CARNEGIE MELLON UNIVERSITY
    Inventors: O Burak Ozdoganlar, Carmel Majidi, Kadri Bugra Ozutemiz, James Wissman
  • Patent number: 11804383
    Abstract: A method for producing a metal-ceramic substrate with a plurality of electrically conductive vias includes: attaching a first metal layer in a planar manner to a first surface side of a ceramic layer; after attaching the first metal layer, introducing a copper hydroxide or copper acetate brine into a plurality of holes in the ceramic layer delimiting a via, to form an assembly; converting the copper hydroxide or copper acetate brine into copper oxide; subjecting the assembly to a high-temperature step above 500° C. in which the copper oxide forms a copper body in the plurality of holes; and after converting the copper hydroxide or copper acetate brine into the copper oxide, attaching a second metal layer in a planar manner to a second surface side of the ceramic layer opposite the first surface side. The copper body produces an electrically conductive connection between the first and the second metal layers.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: October 31, 2023
    Assignee: Infineon Technologies AG
    Inventor: Alexander Roth
  • Patent number: 11800806
    Abstract: A method for fabricating a multi-cell electroacoustic transducer comprises placing a rail layer onto a base, the rail layer comprising a plurality of apertures arranged in an array, filling cavities in the rail layer with a polymer, and applying a flexural plate to the rail layer. The transducer achieves high transmission sensitivity across a broad bandwidth. The transducer may be designed to have a broad or a focused directivity pattern, or may be multi-frequency, depending on the particular application and has a range of applications.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: October 24, 2023
    Assignee: Microtech Medical Technologies Ltd.
    Inventors: Alessandro Stuart Savoia, Giosuè Caliano, Alexander Melamud, Eric S. Tammam
  • Patent number: 11791587
    Abstract: Apparatus and methods for inserting and retention testing an electrically conductive contact in an electrical connector. The method includes the following steps: manually partially inserting the contact into a hole formed inside the electrical connector; inserting the contact further into the hole by pushing the contact along an axis using an insertion tip that is aligned with the axis and that displaces in a first direction along the axis during inserting; and after inserting the contact further into the hole, testing retention of the contact inside the electrical connector by pushing the contact along the axis using a test probe that is aligned with the axis and that displaces in a second direction opposite to the first direction during retention testing. The force exerted by the test probe on the contact is less than a specified contact retention force.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: October 17, 2023
    Assignee: The Boeing Company
    Inventor: Mark E. Hulscher
  • Patent number: 11778911
    Abstract: Aspects of the disclosure provide a method including determining a measurement configuration for one or more piezoelectric devices in an electronic apparatus. The electronic apparatus includes an electronic device mounted on a substrate block using a bonding layer. The one or more piezoelectric devices including a first subset and a second subset are attached to one of the electronic device and the bonding layer. The method includes performing, based on the measurement configuration, a defect measurement on the electronic apparatus by causing the first subset to transmit and the second subset to receive one or more acoustic signals. The method includes determining whether at least one mechanical defect is located in at least one of (i) the bonding layer, (ii) the electronic device, (iii) the substrate block, (iv) interfaces of the electronic device, the bonding layer, and the substrate block based on the received one or more acoustic signals.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: October 3, 2023
    Assignee: OHIO STATE INNOVATION FOUNDATION
    Inventors: Shailesh N. Joshi, Vishnu Baba Sundaresan, Vijay Venkatesh, Srivatsava Krishnan
  • Patent number: 11770901
    Abstract: Provided is a method for operating an electronic component mounting system including component storages including a dry box. The method includes maintaining a material management table including a whereabouts information field for indicating whether an electronic component is stored in the dry box, a target indicator field for indicating whether an electronic component is a moisture management target component, and an exposure time field for indicating an exposure time during the moisture management target component has been in an atmospheric exposure state. The method also includes pausing counting the exposure time when the moisture management target component is stored in the dry box, identifying a moisture management target component of which the exposure time has met or exceeded an exposure limit time based on the whereabouts information table, and notifying the identified moisture management target component to an apparatus.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: September 26, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Norihisa Yamasaki, Yasuhiro Maenishi, Yuji Nakamura
  • Patent number: 11758818
    Abstract: A method of preparing a piezoelectric single crystal with high piezoelectricity and near- perfect transparency. The method includes depositing electrodes on two opposition surfaces of a piezoelectric single crystal which is a ferroelectric crystal; AC-poling the piezoelectric single crystal through the electrodes by repeatedly changing polarity of an AC electric field; and after polarization, removing the electrodes on the two opposition surfaces of the piezoelectric single crystal and then depositing Ag nanowire or indium tin oxide (ITO) as electrodes on the two opposition surfaces of the piezoelectric single crystal. Repeatedly changing the polarity of the polarized electric field can increase the domain size of the ferroelectric crystal, or reduce the domain wall density of the domain structure, thereby improving the transparency of the piezoelectric single crystal having high piezoelectric.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 12, 2023
    Assignees: XI'AN JIAOTONG UNIVERSITY, THE PENNSYLVANIA STATE UNIVERSITY
    Inventors: Fei Li, Chaorui Qiu, Zhuo Xu, Bo Wang, Long-Qing Chen, Shujun Zhang, Thomas R. Shrout