Abstract: Providing for a two-terminal memory cell having intrinsic current limiting characteristic is described herein. By way of example, the two-terminal memory cell can comprise a particle donor layer having a moderate resistivity, comprised of unstable or partially unstable metal compounds. The metal compounds can be selected to release metal atoms in response to an external stimulus (e.g., an electric field, a voltage, a current, heat, etc.) into an electrically-resistive switching medium, which is at least in part permeable to drift or diffusion of the metal atoms. The metal atoms form a thin filament through the switching medium, switching the memory cell to a conductive state. The moderate resistivity of the particle donor layer in conjunction with the thin filament can result in an intrinsic resistance to current through the memory cell at voltages above a restriction voltage, protecting the memory cell from excessive current.

Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.

Abstract: Devices and methods of forming a device are disclosed. The method includes providing a wafer that includes a center insulator layer sandwiched by a top substrate and a bottom substrate. Both sides of the wafer are patterned and etched in sequence to form deep trenches in both substrates. A conductive seed layer is formed on both sides of the wafer in sequence to cover all exposed areas. Both sides of the wafer are electroplated simultaneously to fill both deep trenches with a conductive material. Both sides of the wafer are polished in sequence to form a coplanar surface. A protective layer is deposited on both sides of the wafer in sequence. Selective portions of the protective layer on both sides are patterned and etched in sequence to expose micro bump bonding areas. Micro bumps are formed on both sides of the wafer in sequence to facilitate electrical connection.

Abstract: Disclosed are encapsulation structures, encapsulation methods and display devices of organic electroluminescent devices. The encapsulation structure comprises: a substrate (3); an organic electroluminescent device (2) located on the substrate (3); and at least one film encapsulation layer (1) covering the organic electroluminescent device (2), wherein the film encapsulation layer (1) comprises an inorganic film (11) and a fluorocarbon polymer film (13). The encapsulation structure can effectively improve the film encapsulation layer (1)'s ability to block water and oxygen so as to effectively extend the lifetime of OLED devices.

Abstract: A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.

Abstract: Occurrence of a crosstalk phenomenon in a light-emitting device including a tandem element is suppressed. A light-emitting device includes: lower electrodes over an insulating layer; a partition over a portion between the lower electrodes, which includes an overhang portion over an end portion of each of the lower electrodes; a first light-emitting unit over each of the lower electrodes and the partition; an intermediate layer over the first light-emitting unit; a second light-emitting unit over the intermediate layer; and an upper electrode over the second light-emitting unit. The distance between the overhang portion and each of the lower electrodes is larger than the total thickness of the first light-emitting unit and the intermediate layer over the lower electrode.

Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.

Abstract: An organic light emitting diode display includes a display substrate including an organic light emitting element and a driving circuit part, an encapsulation substrate sealing the display substrate, and a sealing portion between the display substrate and the encapsulation substrate, the sealing portion including a plurality of sealing frame portions around the display substrate, and a first sealing frame portion of the plurality of sealing frame portions being adjacent to a pad portion, wherein at least one of a width of an edge of the sealing portion and a width of the first sealing frame portion is wider than a width of a sealing frame portion other than the first sealing frame portion.

Abstract: A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer.

Abstract: A semiconductor structure includes a first magnetic layer, an insulative oxide layer, an oxygen trapping layer and a cap layer. The insulative oxide layer is over the first magnetic layer. The oxygen trapping layer is over the insulative oxide layer. The oxygen concentration of the oxygen trapping layer is less than an oxygen concentration of the insulative oxide layer. The cap layer is over the oxygen trapping layer.

Abstract: A pixel structure includes a metal oxide semiconductor layer, a first insulating layer, a second insulating layer, a first conductive layer, a passivation layer, a second conductive layer and a pixel electrode. The metal oxide semiconductor layer includes a second semiconductor pattern. The first insulating layer includes a first capacitance dielectric pattern disposed on the second semiconductor pattern. The second insulating layer includes a second capacitance dielectric pattern disposed on the first capacitance dielectric pattern. The first conductive layer includes a electrode pattern disposed on the second capacitance dielectric pattern. The passivation layer covers the first conductive layer. The second conductive layer includes a second electrode disposed on the passivation layer. The second electrode is electrically connected to the second semiconductor pattern. The second electrode is disposed to overlap the electrode pattern.

Abstract: An optoelectronic semiconductor chip includes a p-type semiconductor region, an n-type semiconductor region, and an active layer embodied as a multi-quantum well structure arranged between the p-type semiconductor region and the n-type semiconductor region. The multi-quantum well structure includes a plurality of alternating quantum well layers and barrier layers. At least one barrier layer, which is arranged closer to the p-type semiconductor region than to the n-type semiconductor region, is a high barrier layer that has an electronic band gap that is greater than an electronic band gap of the remaining barrier layers.

Abstract: Embodiments of the invention relate to deposition of a conformal carbon-based material. In one embodiment, the method comprises depositing a sacrificial dielectric layer with a predetermined thickness over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, introducing a hydrocarbon source, a plasma-initiating gas, and a dilution gas into the processing chamber, wherein a volumetric flow rate of hydrocarbon source:plasma-initiating gas:dilution gas is in a ratio of 1:0.5:20, generating a plasma at a deposition temperature of about 300 C to about 500 C to deposit a conformal amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate, and removing the patterned features.

Abstract: A light emitting diode (LED) structure has semiconductor layers, including a p-type layer, an active layer, and an n-type layer. The p-type layer has a bottom surface, and the n-type layer has a top surface though which light is emitted. A copper layer has a first portion electrically connected to and opposing the bottom surface of the p-type layer. A dielectric wall extends through the copper layer to isolate a second portion of the copper layer from the first portion. A metal shunt electrically connects the second portion of the copper layer to the top surface of the n-type layer. P-metal electrodes electrically connect to the first portion, and n-metal electrodes electrically connect to the second portion, wherein the LED structure forms a flip chip. Other embodiments of the methods and structures are also described.

Abstract: Field-effect transistor (FET) stack voltage compensation. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series between the first and terminal and the second terminal. Each switching element has a parameter that is configured to yield a desired voltage drop profile among the connected switching elements. Such a desired voltage drop profile can be achieved by some or all FETs in a stack having variable dimensions such as variable gate width or variable numbers of fingers associated with the gates.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: Magnetic tunnel junction (MTJ) memory bit cells that decouple source line layout from access transistor node size to facilitate reduced contact resistance are disclosed. In one example, an MTJ memory bit cell is provided that includes a source plate disposed above and in contact with a source contact for a source node of an access transistor. A source line is disposed above and in electrical contact with the source plate to electrically connect the source line to the source node. The source plate allows the source line to be provided in a higher metal level from the source and drain contacts of the access transistor such that the source line is not in physical contact with (i.e., decoupled from) the source contact. This allows pitch between the source line and drain column to be relaxed from the width of the source and drain nodes without having to increase contact resistance.

Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.

Abstract: A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.

Abstract: An organic light-emitting display apparatus, including a substrate, a reflection control layer disposed on the substrate and including a metal layer and dielectric layer, a thin-film transistor disposed on the reflection control layer and including an active layer, a gate electrode, a source electrode, and a drain electrode, a storage capacitor disposed on the reflection control layer and including a first electrode and a second electrode, a pixel electrode connected to one of the source electrode and the drain electrode, an intermediate layer disposed on the pixel electrode and including an organic emission layer, an opposite electrode disposed on the intermediate layer, in which a portion of the metal layer of the reflection control layer comprises the first electrode of the storage capacitor.