Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract: An integrable electrochemical capacitor and methods for manufacturing the same are disclosed. The electrochemical capacitor comprises a first electrode comprising a first rigid piece having a first porous portion, a second electrode comprising a second rigid piece having a second porous portion, and an electrolyte in contact with the first porous portion and the second porous portion. The structure allows the electrochemical capacitor to be manufactured without a separator film between the electrodes and is compatible with semiconductor manufacturing technologies. The electrochemical capacitor can also be manufactured within a SOI layer 8.

Abstract: This application relates to MEMS transducer having a membrane layer (101) and at least one variable vent structure (301). The variable vent structure has a vent hole for venting fluid so as to reduce a pressure differential across the membrane layer and a moveable vent cover (302a, 302b) which, at an equilibrium position, at least partly blocks the vent hole. The vent cover is moveable from its equilibrium position in response to a pressure differential across the vent cover so as to vary the size of a flow path through the vent hole. In various embodiments the vent cover comprises at least a first flap section (302a) and a second flap section (302b), the first flap section being hingedly coupled to the side of the vent hole and the second flap section being hingedly coupled to the first flap section so as to be moveable with respect to the first flap section.

Abstract: An interconnect structure and fabrication method are provided. A substrate can include a semiconductor device disposed therein. A porous dielectric layer can be formed on the substrate. A surface treatment can be performed to the porous dielectric layer to form an isolation layer on the porous dielectric layer to prevent moisture absorption of the porous dielectric layer. An interconnect can be formed at least through the isolation layer and the porous dielectric layer to provide electrical connection to the semiconductor device disposed in the substrate.

Abstract: According to one embodiment, a magnetic memory is disclosed. The magnetic memory includes a substrate, an electrode provided on the substrate, a first insulating film surrounding a side surface of the electrode. The first insulating film contains oxygen. The magnetic memory further includes a second insulating film provided between the electrode and the first insulating film, and surrounding the side surface of the electrode. The second insulating film contains nitrogen. A magnetoresistance effect element is provided on the electrode.

Abstract: A method includes depositing a thin film on a first surface of a first substrate and moving a second surface of a second substrate into contact with the thin film such that the thin film is located between the first and second surfaces. The method further includes generating electromagnetic (EM) radiation of a first wavelength, the first wavelength selected such that the thin film absorbs EM radiation at the first wavelength. Additionally, the method includes directing the EM radiation through one of the first and second substrates and onto a region of the thin film until the first and second substrates are fused in the region.

Abstract: A producing method for a diaphragm-type resonant MEMS device includes forming a first silicon oxide film, forming a second silicon oxide film, forming a lower electrode, forming a piezoelectric film, forming an upper electrode, laminating the first silicon oxide film, the second silicon oxide film, the lower electrode, the piezoelectric film, and the upper electrode in this order on a first surface of a silicon substrate, and etching the opposite side surface of the first surface of the silicon substrate by deep reactive ion etching to form a diaphragm structure, in which the proportion R2 of the film thickness t2 of the second silicon oxide film with respect to the sum of the film thickness t1 of the first silicon oxide film and the film thickness t2 of the second silicon oxide film satisfies the following condition: 0.10 ?m?t1?2.00 ?m; and R2?0.70.

Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.

Abstract: A composite is produced by providing a first and a second joining partner, a connecting means, a sealing means, a reactor having a pressure chamber, and a heating element. The two joining partners and the connecting means are arranged in the pressure chamber such that the connecting means is situated between the first joining partner and the second joining partner. A gas-tight region is then produced, in which the connecting means is arranged. Afterward, a gas pressure of at least 20 bar is produced in the pressure chamber outside the gas-tight region. The gas pressure acts on the gas-tight region and presses the first joining partner, the second joining partner and the connecting means together. The joining partners and the connecting means are then heated by means of the heating element to a predefined maximum temperature of at least 210° C. and then cooled.

Abstract: Embodiments of mechanisms of a semiconductor device package and package on package (PoP) structure are provided. The semiconductor device package includes a substrate and a metal pad formed on the substrate. The semiconductor device package further includes a conductive element formed on the metal pad, and the metal pad electrically contacts the conductive element, and at least a portion of the conductive element is embedded in a molding compound, and the conductive element has a recess configured to provide an additional bonding interfacial area.

Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.

Abstract: Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes an upper surface and a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and a Schottky metal layer disposed over the substrate adjacent the gate electrode. The Schottky metal layer includes a Schottky contact electrically coupled to the channel which provides a Schottky junction and at least one alignment mark disposed over the semiconductor substrate. A method for fabricating the semiconductor device includes creating an isolation region that defines an active region along an upper surface of a semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and forming a Schottky metal layer over the semiconductor substrate. Forming the Schottky metal layer includes forming at least one Schottky contact electrically coupled to the channel and providing a Schottky junction, and forming an alignment mark in the isolation region.

Abstract: A liquid crystal display includes a first pixel and a second pixel that extend in a data line direction. The first and second pixels are connected to a same data line, and the first pixel is closer to a data driver than the second pixel. A channel width of a thin film transistor of the first pixel is less than a channel width of a thin film transistor of the second pixel.

Abstract: A semiconductor memory device according to an embodiment includes a memory cell array which has: a first conductive layer which is arranged in a first direction on a first semiconductor layer; a second conductive layer which is arranged in the first direction above the first conductive layer; a columnar second semiconductor layer which extends in the first direction; and a contact unit which electrically connects the first semiconductor layer and the second conductive layer. The contact unit has a first film which contains silicide as a first metal, and is in contact with the first semiconductor layer; and a second film which contains the first metal, is in contact with the first film, and is in contact with the first semiconductor layer with the first film interposed therebetween.

Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

Abstract: The present disclosure provides a resistive random access memory (RRAM) structure. The RRAM structure includes a bottom electrode on a substrate; a resistive material layer on the bottom electrode, the resistive material layer including a defect engineering film; and a top electrode on the resistive material layer.

Abstract: A method of forming high germanium content silicon germanium alloy fins with controlled insulator layer recessing is provided. A silicon germanium alloy (SiGe) layer having a first germanium content is provided on a surface of an insulator layer using a first condensation process. Following the formation of a hard mask layer portion on the SiGe layer, a second condensation process is performed to convert a portion of the SiGe layer into a SiGe fin of a second germanium content that is greater than the first germanium content and other portions of the SiGe layer into a shell oxide structure located on sidewalls of the SiGe fin. After forming a fin placeholder material, a portion of each shell oxide structure is removed, while maintaining a lower portion of each shell oxide structure at the footprint of the SiGe fin.

Abstract: Interconnect fuse structures including a fuse with a necked line segment, as well as methods of fabricating such structures. A current driven by an applied fuse programming voltage may open necked fuse segments to affect operation of an IC. In embodiments, the fuse structure includes a pair of neighboring interconnect lines equidistant from a center interconnect line. In further embodiments, the center interconnect line, and at least one of the neighboring interconnect lines, include line segments of lateral widths that differ by a same, and complementary amount. In further embodiments, the center interconnect line is interconnected at opposite ends of a necked line segment. In further embodiments, the necked line segment is fabricated with pitch-reducing spacer-based patterning process.