Patents Examined by John C. Ingham
  • Semiconductor devices and methods of fabricating the same
    Patent number: 9640658
    Abstract: A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: May 2, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Hyuk Kim, Dongsuk Shin, Myungsun Kim, Hoi Sung Chung
  • Deep gate-all-around semiconductor device having germanium or group III-V active layer
    Patent number: 9640671
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Solid-state imaging devices with enhanced angular response
    Patent number: 9634049
    Abstract: A solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements arranged into a pixel array. A color filter layer including a plurality of color filter segments is disposed above the photoelectric conversion elements. A partition grid includes a plurality of partitions, and each of the partitions is disposed between two adjacent color filter segments. The color filter layer and the partition grid are disposed in the same layer. In addition, the partitions include a first partition disposed at a center line of the pixel array and a second partition disposed at an edge of the pixel array. The second partition has a top width that is larger than the top width of the first partition.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: April 25, 2017
    Assignee: Visera Technologies Company Limited
    Inventors: Chih-Chieh Chang, Chi-Han Lin
  • FinFET and method of fabricating the same
    Patent number: 9634104
    Abstract: A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Donald Y. Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Thin film transistor and method of manufacturing the same, array substrate and display apparatus
    Patent number: 9634033
    Abstract: The present disclosure discloses a thin film transistor comprising: an active layer; an etching barrier layer arranged on the active layer and formed with a plurality of via holes therein; and a source electrode and a drain electrode arranged on the etching barrier layer, wherein the source electrode comprises at least two sub source electrodes and the drain electrode comprises at least two sub drain electrodes; and the sub source electrodes and the sub drain electrodes constitute at least two parallel sub-switches, each of which comprises a sub source electrode and a sub drain electrode, and the sub source electrode and the sub drain electrode are electrically connected to the active layer through the via holes in the etching barrier layer, respectively. The present disclosure further discloses a method of manufacturing a thin film transistor, an array substrate and a display apparatus.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: April 25, 2017
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Zhenfei Cai, Zhengwei Chen
  • Third type of metal gate stack for CMOS devices
    Patent number: 9634006
    Abstract: A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Sameer H. Jain, Viraj Y. Sardesai, Keith H. Tabakman
  • Device electrode formation using metal sheet
    Patent number: 9627351
    Abstract: A solution for packaging a two terminal device, such as a light emitting diode, is provided. In one embodiment, a method of packaging a two terminal device includes: patterning a metal sheet to include a plurality of openings; bonding at least one two terminal device to the metal sheet, wherein a first opening corresponds to a distance between a first contact and a second contact of the at least one two terminal device; and cutting the metal sheet around each of the least one two terminal device, wherein the metal sheet forms a first electrode to the first contact and a second electrode to the second contact.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 18, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Yuri Bilenko, Michael Shur, Remigijus Gaska, Alexander Dobrinsky
  • Organic light emitting display device having dummy sub-pixels
    Patent number: 9627454
    Abstract: Provided are an organic light emitting display device, the display device including: a substrate defined into a display area and a non-display area; sub-pixels formed on the display area of the substrate; and dummy sub-pixels formed on the non-display area of the substrate, the dummy sub-pixels have a different shape for each position of the non-display area.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 18, 2017
    Assignee: LG Display Co., Ltd.
    Inventors: Kyungsu Lee, Incheol Park, Jimin Choi
  • Post spacer, display panel and display device
    Patent number: 9625766
    Abstract: The present invention relates to the technical field of display, and in particular to a post spacer, a display panel and a display device. The post spacer includes a support post and a support pillow, wherein the support pillow is formed of a plurality of sub-pillows dispersedly arranged below the bottom of the support post. Since the post spacer is provided with the support pillows dispersedly arranged below the bottom of the support post, the bottom of the support post can be more uniformly stressed, and the support pillow can further provide a certain antiskid effect. Therefore, the post spacer of the present invention has a better supporting effect and can effectively avoid Mura faults.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 18, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingxing Song, Chaohuan Hsu, Zhengwei Chen, Zhenfei Cai
  • Organic light emitting diode display having reaction-blocked common voltage line
    Patent number: 9627642
    Abstract: An organic light emitting diode (“OLED”) display includes: a substrate divided into a pixel area, and a peripheral area enclosing the pixel area; an OLED in the pixel area and including a first electrode, an organic emission layer and a second electrode; a common voltage line in the peripheral area and transmitting a common voltage to the second electrode; and a reaction blocking part overlapping the common voltage line.
    Type: Grant
    Filed: December 15, 2013
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sang-Mok Hong, Gun-Tae Park, Ho-In Lee
  • Resistive switching memory
    Patent number: 9627441
    Abstract: In one embodiment of the present invention, a memory cell includes a first resistive switching element having a first terminal and a second terminal, and a second resistive switching element having a first terminal and a second terminal. The memory further includes a three terminal transistor, which has a first terminal, a second terminal, and a third terminal. The first terminal of the three terminal transistor is coupled to the first terminal of the first resistive switching element. The second terminal of the three terminal transistor is coupled to the first terminal of the second resistive switching element. The third terminal of the three terminal transistor is coupled to a word line.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: April 18, 2017
    Assignee: ADESTO TECHNOLOGIES CORPORATION
    Inventor: Michael A. Van Buskirk
  • Semiconductor devices having work function adjusting films with chamfered top surfaces
    Patent number: 9627380
    Abstract: A semiconductor device includes an interlayer insulating film formed on a substrate and including a trench, a gate insulating film formed in the trench, a work function adjusting film formed on the gate insulating film in the trench along sidewalls and a bottom surface of the trench, and including an inclined surface having an acute angle with respect to the sidewalls of the trench, and a metal gate pattern formed on the work function adjusting film in the trench to fill up the trench.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Youn Kim, Kwang-You Seo
  • Display device having a furrow structure on a light blocking member
    Patent number: 9618801
    Abstract: Exemplary embodiments relate to a display device, an optical mask, and a method for manufacturing a display device using the same. The display device including: a first substrate and a second substrate facing the first substrate; a thin film transistor disposed on the first substrate; a first insulating layer disposed on the thin film transistor; and a light blocking member disposed on the first insulating layer. The light blocking member includes a spacer for maintaining a cell gap between the first substrate and the second substrate and a main light blocking portion having an upper surface that is lower than an upper surface of the spacer, and the light blocking member further includes a furrow at a border between the spacer and the main light blocking portion, the furrow having a surface lower than the upper surface of the main light blocking portion.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 11, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Soon Jang, Hee Ra Kim, Yi Seop Shim, Chul Huh
  • Memory cells formed with sealing material
    Patent number: 9620713
    Abstract: Memory cells, arrays of memory cells, and methods of forming the same with sealing material on sidewalls thereof are disclosed herein. One example of forming a memory cell includes forming a stack of materials, forming a trench to a first depth in the stack of materials such that a portion of at least one of the active storage element material and the active select device material is exposed on sidewalls of the trench. A sealing material is formed on the exposed portion of the at least one of the active storage element material and the active select device material and the trench is deepened such that a portion of the other of the at least one of the active storage element material and the active select device material is exposed on the sidewalls of the trench.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: April 11, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Fabio Pellizzer
  • Semiconductor device and method of fabricating the same
    Patent number: 9614068
    Abstract: A semiconductor device includes a first active region, a field insulating layer disposed in the first active region, a first nanowire pattern disposed on the first active region and extended in a first direction, and a first gate disposed on the first active region and extended in a second direction crossing the first direction. The first gate covers the first nanowire pattern. The semiconductor device further includes a source or drain epitaxial layer disposed on at least one side of the first nanowire pattern. The first gate includes a first region disposed on the first nanowire pattern and having a first width, and a second region disposed beneath the first nanowire pattern and having a second width wider than the first width.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kang-Ill Seo
  • Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof
    Patent number: 9607938
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: MinKyung Kang, YoungDal Roh, Dong Ju Jeon, KyoungHee Park
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 9608057
    Abstract: A MOS semiconductor device has a MOS structure, including a p? region that surrounds an n+-type source region and has a net doping concentration lower than a concentration of a p-type impurity in a surface of a p-type well region, and a gate electrode that is provided on top of the surface of the p-type well region sandwiched between the n+-type source region and a surface layer of an n? layer, with a gate insulator disposed between the p-type well region and the gate electrode. This configuration can make the gate insulator thicker without increasing a gate threshold voltage, and help improve the reliability of the gate insulator and reduce the gate capacitance.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 28, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shuhei Tatemichi, Takeyoshi Nishimura, Yasushi Niimura, Masanori Inoue
  • Schottky-barrier device and related semiconductor product
    Patent number: 9608056
    Abstract: In one general aspect, a power rectifier device can include a drift layer including silicon carbide of n-type conductivity, and a Schottky electrode disposed on the drift layer where the Schottky electrode and a surface of the drift layer can provide a Schottky contact. The power rectifier device can also include an array of p-type regions disposed underneath the Schottky electrode.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: March 28, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Andrei Konstantinov
  • Probe pad design to reduce saw defects
    Patent number: 9607926
    Abstract: An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: March 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj Jain
  • Ultra-high pressure doping of materials
    Patent number: 9601641
    Abstract: A method and apparatus is disclosed for doping a semiconductor substrate with a dopant concentration greater than 1020 atoms per cubic centimeter. The method is suitable for producing an improved doped wide bandgap wafer for power electronic devices, photo conductive semiconductor switch, or a semiconductor catalyst.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: March 21, 2017
    Assignee: AppliCote Associates, LLC
    Inventors: Nathaniel R Quick, Michael C Murray