Abstract: The present invention discloses a thin film transistor (TFT), an array substrate, and fabrication methods thereof, and a display device. The TFT includes a gate, an oxide active layer, a source, and a drain formed on a substrate, wherein a source and drain transition layer is provided between the oxide active layer and the source, the drain. One patterning process is reduced and one mask process is saved through forming the source and drain transition layer between the oxide active layer and the source, the drain, thus effectively simplifying the fabrication procedure. At the same time, the additionally provided source and drain transition layer may prevent the oxide active layer from being corroded during etching, also effectively reduce threshold voltage (Vth) drift of the TFT, improve Ion (on-state current) /Ioff (off-state current), and enhance thermal stability.

Abstract: A semiconductor device may include a drift region having a first conductivity type, a source region having the first conductivity type, and a well region having a second conductivity type disposed adjacent to the drift region and adjacent to the source region. The well region may include a channel region that has the second conductivity type disposed adjacent to the source region and proximal to a surface of the semiconductor device cell. The channel region may include a non-uniform edge that includes at least one protrusion.

Abstract: A method for fabricating a semiconductor device includes forming a pre-fin extending in a first direction, the pre-fin including first, second, and third regions, forming first and second gates on the pre-fin to extend in a second direction intersecting the first direction, the first and second gates being spaced apart from each other in the first direction and overlapping with the first and second regions, respectively, forming first and second dummy spacers on the first and second regions, respectively to form a first trench in the third region that exposes the third region, forming a second trench by etching the exposed third region using the first and second dummy spacers as masks to separate the pre-fin into first and second active fins corresponding to the first and second regions, respectively, forming a dummy gate by filling the first and second trenches and removing the first and second dummy spacers.

Abstract: Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur.

Abstract: A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Abstract: In some embodiments, the present disclosure relates to a MEMs (microelectromechanical system) package device having a getter layer. The MEMs package includes a first substrate having a cavity located within an upper surface of the first substrate. The cavity has roughened interior surfaces. A getter layer is arranged onto the roughened interior surfaces of the cavity. A bonding layer is arranged on the upper surface of the first substrate on opposing sides of the cavity, and a second substrate bonded to the first substrate by the bonding layer. The second substrate is arranged over the cavity. The roughened interior surfaces of the cavity enables more effective absorption of residual gases, thereby increasing the efficiency of a gettering process.

Abstract: A method for forming an aluminum nitride-based film on a substrate by plasma-enhanced atomic layer deposition (PEALD) includes: (a) forming at least one aluminum nitride (AlN) monolayer and (b) forming at least one aluminum oxide (AlO) monolayer, wherein steps (a) and (b) are alternately conducted continuously to form a laminate. Steps (a) and (b) are discontinued before a total thickness of the laminate exceeds 10 nm, preferably 5 nm.

Abstract: Optoelectronic modules include a silicon substrate in which or on which there is an optoelectronic device. An optics assembly is disposed over the optoelectronic device, and a spacer separates the silicon substrate from the optics assembly. Methods of fabricating such modules also are described.

Abstract: Provided is a semiconductor device including a plurality of trenches, including an emitter electrode; a floating layer of a first conduction type provided between adjacent trenches; and a low-dielectric-constant film provided between the floating layer and the emitter electrode, in which a dielectric constant of the low-dielectric-constant film is less than 3.9. Also provided is a semiconductor device further including a gate electrode formed in the trenches, in which capacitance between the gate electrode and the floating layer is greater than capacitance between the emitter electrode and the floating layer.

Abstract: A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors.

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate.

Abstract: A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate with a semiconductor layer, forming a first gate electrode over the semiconductor layer, forming a second gate electrode over the semiconductor layer, forming a mask layer between the first and second gate electrodes, etching a cavity into the semiconductor layer between the first and second gate electrodes using the mask layer as an etching mask, and forming a semiconductor material in the etched cavities.

Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

Abstract: An electromechanical device comprises a substrate structure, a set of electrodes, one or more anchor trenches, and one or more multi-faced components. For example, each of the one or more multi-faced components comprises an isolation region formed on a first portion of the surface of the component, a high resistance region formed on a second portion of the surface of the component, and a low resistance region formed on a third portion of the surface of the component. For example, the synapse device is configured to provide an analog resistive output, ranging between the high resistance region and the low resistance region, from at least one of the set of electrodes in response to a pulsed voltage input to at least another one of the set of electrodes.

Abstract: A spin transfer torque magnetic junction includes a magnetic reference layer structure with magnetic anisotropy perpendicular to a substrate plane. A laminated magnetic free layer comprises at least three sublayers (e.g. sub-layers of CoFeB, CoPt, FePt, or CoPd) having magnetic anisotropy perpendicular to the substrate plane. Each such sublayer is separated from an adjacent one by a dusting layer (e.g. tantalum). An insulative barrier layer (e.g. MgO) is disposed between the laminated free layer and the magnetic reference layer structure. The spin transfer torque magnetic junction includes conductive base and top electrodes, and a current polarizing structure that has magnetic anisotropy parallel to the substrate plane. In certain embodiments, the current polarizing structure may also include a non-magnetic spacer layer (e.g. MgO, copper, etc).

Abstract: A switch includes a graphene structure extending longitudinally between a pair of electrodes and being conductively connected to both electrodes of said pair. First and second electrically conductive structures are laterally outward of the graphene structure and on opposing sides of the graphene structure from one another. Ferroelectric material is laterally between the graphene structure and at least one of the first and second electrically conductive structures. The first and second electrically conductive structures are configured to provide the switch into “on” and “off” states by application of an electric field across the graphene structure and the ferroelectric material. Other embodiments are disclosed, including components of integrated circuitry which may not be switches.

Abstract: The performance of a solid state image sensor which is formed by performing divided exposure that exposes the entire chip by a plurality of times of exposure and in which each of a plurality of pixels arranged in a pixel array portion has a plurality of photodiodes is improved. In the divided exposure performed when the solid state image sensor is manufactured, a dividing line that divides an exposure region is defined to be located between a first photodiode and a second photodiode aligned in a first direction in an active region in a pixel and is defined to be along a second direction perpendicular to the first direction.

Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: According to one embodiment, a semiconductor memory device includes a magnetic tunnel junction (MTJ) element includes a first magnetic layer, a second magnetic layer and a non-magnetic layer between the first and second magnetic layers, a contact layer formed underneath the MTJ element, the contact layer being formed of a first material, and a first layer formed around the contact layer, wherein the first layer in contact with a side surface of the contact layer, has a first width extending parallel to a stacking direction of the MTJ element, and a second width extending perpendicularly to the direction of extension of the first width, the second width being less than the first width.