Abstract: A magnetic element is disclosed wherein a composite seed layer such as TaN/Mg enhances perpendicular magnetic anisotropy (PMA) in an overlying magnetic layer that may be a reference layer, free layer, or dipole layer. The first seed layer is selected from one or more of Ta, Zr, Nb, TaN, ZrN, NbN, and Ru. The second seed layer is selected from one or more of Mg, Sr, Ti, Al, V, Hf, B, and Si. A growth promoting layer made of NiCr or an alloy thereof may be inserted between the seed layer and magnetic layer. The magnetic element has thermal stability to at least 400° C.

Abstract: A method is disclosed for forming a semiconductor device. A first opening is formed for an STI on a semiconductor substrate and a first process is performed to deposit first oxide into the first opening. A second opening is formed to remove a portion of the first oxide from the first opening and second process(es) is/are performed to deposit second oxide into the second opening and over a remaining portion of the first oxide. A portion of the semiconductor device is formed over a portion of a surface of the second oxide. A semiconductor device includes an STI including a first oxide formed in a lower portion of a trench of the STI and a second oxide formed in an upper portion of the trench and above the first oxide. The semiconductor device includes a portion of the semiconductor device formed over a portion of the second oxide.

Abstract: A thin film transistor panel includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, an organic semiconductor overlapping with the gate electrode, a source electrode and a drain electrode electrically connected to the organic semiconductor, a fluorine-containing organic insulation layer covering the organic semiconductor, and a photosensitive organic insulation layer covering the fluorine-containing organic insulation layer.

Abstract: A method of forming a sensor component includes forming a first layer over a sensor pad of a sensor of a sensor array. The first layer includes a first inorganic material. The method further includes forming a second layer over the first layer. The second layer includes a polymeric material. The method also includes forming a third layer over the second layer, the third layer comprising a second inorganic material; patterning the third layer; and etching the second layer to define a well over the sensor pad of the sensor array.

Abstract: Fabricating a wafer-scale spacer/optics structure includes replicating optical replication elements and spacer replication sections directly onto an optics wafer (or other wafer) using a single replication tool. The replicated optical elements and spacer elements can be composed of the same or different materials.

Abstract: Embodiments of the present invention disclose a display back plate. The display back plate comprises: an array substrate; and a pixel define layer formed on the array substrate and for defining an organic light emitting unit. An accommodation space is provided in the pixel define layer and a water absorbent material is provided within the accommodation space; the accommodation space has an opening formed in an upper surface and/or a lower surface of the pixel define layer; and the accommodation space is separated from the organic light emitting unit such that the water absorbent material within the accommodation space is spaced away from the organic light emitting unit. Embodiments of the present invention enable absorption of water vapor inside the organic light emitting display device, to prevent the adverse affection of water vapor on performance of the organic light emitting display device, so as to prolong service life of the organic light emitting display device.

Abstract: A semiconductor device, and a method for manufacturing the same, comprises a source/drain region formed using a solid phase epitaxy (SPE) process to provide partially isolated source/drain transistors. Amorphous semiconductor material at the source/drain region is crystallized and then shrunk through annealing, to apply tensile stress in the channel direction.

Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.

Abstract: The present application relates to a reinforcing structure for reinforcing a stack of layers in a semiconductor component, wherein at least one reinforcing element having at least one integrated anchor-like part, is provided. The basic idea is to reinforce bond pad structures by providing a better mechanical connection between the layers below an advanced underbump metallization (BUMA, UBM) by providing reinforcing elements under the UBM and/or BUMA layer.

Abstract: A silicon interposer with redundant thru-silicon vias. The silicon interposer includes a first trace structure on a first side of the interposer and a second trace structure on a second side of the interposer. The silicon interposer also includes at least two redundant thru-silicon vias connecting the first trace structure to the second trace structure.

Abstract: A light emitting device includes a substantially cuboid package and a light emitting element. The package is made up of a molded article, and first and second leads each embedded in the molded article. The first lead has a first terminal component exposed at the boundary between a first side face, a bottom face, and a rear face contiguous with the bottom face and opposite a light emission face. The second lead has a second terminal component exposed at the boundary between a second side face opposite the first side face, the bottom face, and the rear face. The first terminal component has a first terminal concavity whose opening is contiguous with the first side face, the bottom face, and the rear face. The second terminal component has a second terminal concavity whose opening is contiguous with the second side face, the bottom face, and the rear face.

Abstract: A fin field-effect transistor (finFET) and a method of forming are provided. A gate electrode is formed over one or more fins. Notches are formed in the ends of the gate electrode along a base of the gate electrode. Optionally, an underlying dielectric layer, such as a shallow trench isolation, may be recessed under the notch, thereby reducing gap fill issues.

Abstract: A method of forming an OTPROM capable of storing twice the number of bits as a conventional OTPROM without increasing the overall size of the device is provided. Embodiments include forming a OTPROM, the OTPROM array having a plurality of formed devices; receiving a binary code to program the OTPROM array; separating the binary code into a first part and a second part; programming each device with one of four data storage states by: forming a gate oxide layer of each device to a thickness corresponding to the first part of the binary code, and selectively applying a TDDB stress to the gate oxide layer corresponding to the second part of the binary code; detecting a Idsat level discharged by each device with a multi-bit sense amplifier; and reading the state of each device based on the detected Idsat level.

Abstract: A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.

Abstract: A cracks propagation preventing, polarization film attaches to outer edges of a lower inorganic layer of an organic light emitting diodes display where the display is formed on a flexible substrate having the lower inorganic layer blanket formed thereon. The organic light emitting diodes display further includes a display unit positioned on the inorganic layer and including a plurality of organic light emitting diodes configured to display an image, and a thin film encapsulating layer covering the display unit and joining with edges of the inorganic layer extending beyond the display unit.

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a substrate; forming a well region on the substrate; forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating layer and a first gate electrode formed on the gate insulating layer, wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region; wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern is defined as a second region; performing ion implantation on the first region such that the first region has a first conductivity type, and performing ion implantation on the second region such that the second region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

Abstract: This disclosure provides systems, methods, and apparatus related to locally doping two-dimensional (2D) materials. In one aspect, an assembly including a substrate, a first insulator disposed on the substrate, a second insulator disposed on the first insulator, and a 2D material disposed on the second insulator is formed. A first voltage is applied between the 2D material and the substrate. With the first voltage applied between the 2D material and the substrate, a second voltage is applied between the 2D material and a probe positioned proximate the 2D material. The second voltage between the 2D material and the probe is removed. The first voltage between the 2D material and the substrate is removed. A portion of the 2D material proximate the probe when the second voltage was applied has a different electron density compared to a remainder of the 2D material.

Abstract: A method of manufacturing an organic light-emitting display device is provided. The method includes forming a pixel electrode, forming a hydrophobic material layer on the pixel electrode, wherein the hydrophobic material layer includes a hydrophobic material, forming a pixel-defining layer by patterning the hydrophobic material layer, so as to expose at least a portion of the pixel electrode, and removing the hydrophobic material on the exposed portion of the pixel electrode using surface treatment.