Abstract: A high-voltage semiconductor device includes a semiconductor substrate, a gate structure, a drain, an insulation structure, and a plurality of conductive structures. The insulation structure is disposed in the semiconductor substrate and disposed between the gate structure and the drain. The insulation structure includes a plurality of insulation units disposed separately from one another. Each of the conductive structures is embedded in one of the insulation units.

Abstract: High bandgap alloys for high efficiency optoelectronics are disclosed. An exemplary optoelectronic device may include a substrate, at least one Al1-xInxP layer, and a step-grade buffer between the substrate and at least one Al1-xInxP layer. The buffer may begin with a layer that is substantially lattice matched to GaAs, and may then incrementally increase the lattice constant in each sequential layer until a predetermined lattice constant of Al1-xInxP is reached.

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways.

Abstract: An optical through silicon via is formed in a silicon substrate of an integrated circuit. A photo detector is formed within the integrated circuit and is optically coupled to a first side of the optical through silicon via. A light generating source optically coupled to a second side of the optical through silicon via is provided. The photo detector is configured to receive a light, generated by the light generating source, propagating through the optical through silicon via. The light, generated by the light generating source, is controlled by a signal generated by a signal generating source.

Abstract: A TSV via structure comprising an upper part made on the side of the front face of a substrate in which electronic components are located and a lower part with height and cross-section smaller than the height and cross-section the upper part, the arrangement of the connection element in the substrate being such that it releases stresses generated by the different materials of said structure.

Abstract: A method of fabricating a semiconductor device includes forming an insulation pattern including a mask region and an open region on a gallium nitride substrate, growing gallium nitride semiconductor layers to cover the insulation pattern, and patterning the semiconductor layers to form a plurality of semiconductor stacks separated from each other, the plurality of semiconductor stacks being electrically isolated from the gallium nitride substrate by the insulation pattern.

Abstract: Vertical power MOSFETs having a super junction are devices capable of having a lower on resistance than other vertical power MOSFETs. Although they have the advantage of high-speed switching due to rapid depletion of an N type drift region at the time of turn off in switching operation, they are likely to cause ringing. A vertical power MOSFET having a super junction structure provided by the present invention has, in the surface region of a first conductivity type drift region under a gate electrode, an undergate heavily doped N type region having a depth shallower than that of a second conductivity type body region and having a concentration higher than that of the first conductivity type drift region.

Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.

Abstract: A frequency multiplier based on a low dimensional semiconductor structure, including an insulating substrate layer, a semiconductor conducting layer arranged on the surface of the insulating substrate layer, an insulating protective layer arranged on the surface of the semiconductor conducting layer, an insulating carving groove penetrating the semiconductor conducting layer, an inlet electrode arranged on the side surface of the semiconductor conducting layer, and an outlet electrode arranged on the side surface corresponding to the access electrode is provided. The semiconductor conducting layer comprises two two-dimensional, quasi-one-dimensional, or one-dimensional current carrying channels near to and parallel to each other. The frequency multiplier has advantages that the structure is simple, the process is easy to implement, no extra filter circuit needs to be added, dependence on material characteristics is little, and the selection range of materials is wide.

Abstract: A light-emitting element which has low driving voltage and high emission efficiency is provided. The light-emitting element includes, between a pair of electrodes, a hole-transport layer and a light-emitting layer over the hole-transport layer. The light-emitting layer contains a first organic compound having an electron-transport property, a second organic compound having a hole-transport property, and a light-emitting third organic compound converting triplet excitation energy into light emission. A combination of the first organic compound and the second organic compound forms an exciplex. The hole-transport layer contains at least a fourth organic compound whose HOMO level is lower than or equal to that of the second organic compound and a fifth organic compound whose HOMO level is higher than that of the second organic compound.

Abstract: A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.

Abstract: A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.

Abstract: The organic electroluminescence element of the present invention includes: a first substrate; a second substrate facing the first substrate; an element member between the first and second substrates; first and second extension electrodes on first and second inner surfaces of the first and second substrates facing the element member; and an insulating member having an electrically insulating property. The element member includes: a functional layer including a light-emitting layer and having first and second surfaces in a thickness direction; and first and second electrode layers on the respective first and second surfaces of the functional layer. The element member is between the first and second extension electrodes such that parts of the first and second electrode layers are in contact with the first and second extension electrodes respectively. The insulating member is between the first and second inner surfaces of the respective first and second substrates.

Abstract: A 3D nonvolatile memory device including memory cells vertically stacked is disclosed. Word lines are integrally formed to be elongated over adjacent cell regions spaced apart from each other, and portions of the word lines between the cell regions are partially etched in a stepped shape to form word line contact regions.

Abstract: Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate in which at least three pixel areas are defined, a first electrode and a hole transporting layer formed on the substrate, an light-emitting material layer formed on the hole transporting layer in each of the pixel areas, and an electron transporting layer and a second electrode formed on the light-emitting material layer. An optical assistant transporting layer is formed on the light-emitting material layer at a position corresponding to one of the pixel areas, and formed of an electron transporting material. Accordingly, provided can be a high-resolution organic light emitting display device that solves an imbalance of electric charges and has an excellent light output efficiency and an enhanced service life.

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract: The method of manufacturing a device substrate includes forming a surface modifying layer on a process substrate. The surface modifying layer has a different hydrophobicity from that of the process substrate. The process substrate is disposed on a carrier substrate. The surface modifying layer is disposed between the process substrate and the carrier substrate. A device is formed on the process substrate. The process substrate is separated from the carrier substrate.

Abstract: A semiconductor package is disclosed, which includes: a circuit board; a carrier disposed on the circuit board; an RF chip disposed on the carrier; a plurality of high level bonding wires electrically connecting electrode pads of the RF chip and the circuit board; and an encapsulant formed on the circuit board for encapsulating the carrier, the high level bonding wires and the RF chip. The present invention positions the RF chip at a high level so as to facilitate element arrangement and high frequency wiring on the circuit board, thereby achieving a highly integrated wireless SiP (System in Package) module.

Abstract: A method of manufacturing an organic light-emitting diode display includes disposing a first electrode on a substrate on which a plurality of transistors is disposed, disposing a pixel definition layer on the substrate to cover a part of the first electrode, disposing a solvent layer on the first electrode, disposing an organic layer on the pixel definition layer and the solvent layer, removing the solvent layer and disposing a second electrode on the organic layer.

Abstract: Semiconductor packages including stacked semiconductor chips are provided. The semiconductor packages may include first semiconductor chips and a second semiconductor chip that are stacked sequentially on a board. The semiconductor packages may also include a wiring layer on the memory chips and the wiring layer may include redistribution patterns and redistribution pads. Each of the memory chips may include a data pad. The data pads of the first semiconductor chips may be electrically connected to the board via the second semiconductor chip, some of redistribution patterns, and some of redistribution pads.