Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.

Abstract: A wafer transport method is provided. The wafer transport method includes loading an initial carrier containing a first wafer and a second wafer on a first semiconductor apparatus, and processing the first wafer by the first semiconductor apparatus, and loading the first wafer into a first carrier disposed on the first semiconductor apparatus. The wafer transport method also includes processing the second wafer by the first semiconductor apparatus, and loading the second wafer into a second carrier disposed on the first semiconductor apparatus. The wafer transport method further includes processing the first wafer by a second semiconductor apparatus, and loading the first wafer into an integration carrier disposed on the second semiconductor apparatus. The wafer transport method further includes processing the second wafer by the second semiconductor apparatus, and loading the second wafer into the integration carrier disposed on the second semiconductor apparatus.

Abstract: A thin film transistor array panel includes a first insulation substrate, a gate line and a data line which are positioned on the first insulation substrate, are insulated from each other, and cross each other, a thin film transistor connected to the gate line and the data line, an organic film positioned on the thin film transistor, a second passivation layer which is positioned on the organic film and defines a plurality of second openings therein, a common electrode positioned on the second passivation layer, and a pixel electrode positioned in the plurality of second openings, where a thickness of the common electrode is larger than a thickness of the pixel electrode.

Abstract: An LED device with improved angular color performance has a silicone lens shaped as a portion of a sphere. The lens is molded over an array of LED dies disposed on the upper surface of a substrate. Phosphor particles are disbursed throughout the material used to mold the lens. The distance between farthest-apart edges of the LED dies is more than half of the length that the lens extends over the surface of the substrate. The distance from the top of the lens dome to the surface of the substrate is between 57% and 73% of the radius of the sphere. Shaping the lens as the top two thirds of a hemisphere reduces the non-uniformity in the emitted color such that neither of the CIE color coordinates x or y of the color changes more than 0.004 over all emission angles relative to the surface of the substrate.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a power device well in a semiconductor substrate, a logic device well in the substrate and spaced apart from the power device well by a separation region of the substrate, and a minority carrier conversion structure including a first doped region of a first conductivity type in the separation region, a second doped region of a second conductivity type in the separation region and a conducting layer connecting the first and second doped regions. The second doped region includes a first part interposed between the first doped region and the power device well and a second part interposed between the first doped region and the logic device well.

Abstract: A pixel structure located on a periphery of a display module includes a substrate, a flexible circuit board and a plurality of LED chips. The substrate has at least one scribing tolerance reserving zone and a display unit mounting zone. The flexible circuit board is disposed on the display unit mounting zone of the substrate. The LED chips are mounted on the flexible circuit board.

Abstract: The present disclosure relates to an electrode manufacturing method, and a fuse device and manufacturing method therefor. The fuse device includes a fuse element including a phase change material, and a first electrode formed in contact with the fuse element. The phase change material may include doped or undoped chalcogenide. The first electrode may have a sublithographic dimension at a portion where the first electrode contacts the fuse element. When the phase change material has a layer thickness less than or equal to about 30 nm, and a pulse current less than or equal to about 3 mA is applied to the fuse element via the first electrode, the fuse element may undergo a phase change, so as to convert the fuse device into a blow-out state.

Abstract: An organic light emitting diode, including: a substrate; a first cavity electrode in a first micro-cavity region of the substrate; a first transparent electrode of a first thickness in the first micro-cavity region, the first transparent electrode overlaps beyond a first side of the first cavity electrode; a first emissive layer in electrical connection with the first transparent electrode; and a cathode layer on the first emissive layer.

Abstract: A display device and method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a display area and a non-display area surrounding the display area. The display device also includes a first insulating layer formed in the non-display area, a first metal layer formed over the first insulating layer, and a second insulating layer formed over the first metal layer. A plurality of openings are formed in each of the first and second insulating layers and the first metal layer. The display device further includes a sealing member formed over the second insulating layer. The sealing member includes a plurality of coupling portions filling the openings and a groove is formed in a side wall of each of openings.

Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.

Abstract: A dual damascene structure with an embedded liner and methods of manufacture are disclosed. The method includes forming a dual damascene structure in a substrate. The method further includes reflowing a seed layer such that material of the seed layer flows into a via of the dual damascene structure. The method further includes forming a liner material on the material over or within the via of the dual damascene structure. The method further includes filling any remaining portions of the via and a trench of the dual damascene structure with additional material.

Abstract: OLEDs containing a stacked hybrid architecture including a phosphorescent organic emissive unit and two fluorescent organic emissive units are disclosed. The stacked hybrid architecture includes a plurality of electrodes and a hybrid emissive stacked disposed between at least two of the electrodes. The stack contains at least three emissive units and at least two charge generation layers. At least one of the three emissive units is a phosphorescent organic emissive unit and at least two of the three emissive units are fluorescent organic emissive units. More specifically, the two fluorescent organic emissive units may be blue organic emissive units that emit light from the same or different color regions.

Abstract: A method of fabricating a thin film transistor including following steps is provided. Sequentially form a semiconductor layer, a metal layer and an auxiliary layer on a substrate. Perform a crystallization process to transform the semiconductor layer into an active layer after the metal layer and the auxiliary layer are disposed on the semiconductor layer. After the active layer is formed, pattern the metal layer to form a source and a drain. Form a gate insulator and a gate. The gate insulator is disposed between the gate and the source and drain.

Abstract: A method of minimizing a seam effect of a deposited TEOS oxide film during a trench filling process performed on a semiconductor substrate in a semiconductor substrate plasma processing apparatus comprises supporting a semiconductor substrate on a pedestal in a vacuum chamber thereof. Process gas including TEOS, an oxidant, and argon is flowed through a face plate of a showerhead assembly into a processing region of the vacuum chamber. RF energy energizes the process gas into a plasma wherein TEOS oxide film is deposited on the semiconductor substrate so as to fill at least one trench thereof. The argon is supplied in an amount sufficient to increase the electron density of the plasma such that the deposition rate of the TEOS oxide film towards the center of the semiconductor substrate is increased and the seam effect of the deposited TEOS oxide film in the at least one trench is reduced.

Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel supply layer that induces a two-dimensional electron gas (2DEG) in a channel layer, a source electrode and a drain electrode that are at sides of the channel supply layer, a depletion-forming layer that is on the channel supply layer and contacts the source electrode, a gate insulating layer on the depletion-forming layer, and a gate electrode on the gate insulating layer. The depletion-forming layer forms a depletion region in the 2DEG.

Abstract: In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured to enable a transistor or a transistor of an SCR responsively to an input voltage having a value that is no less than the trigger value of the ESD device.

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract: Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract: An organic light emitting display device includes a first electrode formed on a substrate and being a reflective electrode, a second electrode facing the first electrode and being a semi-transparent electrode, and red, green and blue emission layers formed between the first and second electrodes, wherein a maximum electroluminescent peak of the redemission layer and a maximum photoluminescence peak of a host included in the red emission layer satisfy Equation 1 below: REDEL?max?RHPL?max?120 nm??<Equation 1> wherein REDEL?max is a maximum electroluminescent peak of the red emission layer, and RHPL?max is a maximum photoluminescence peak of a red host included in the red emission layer.