Abstract: In a connection-oriented communications network, a source node selects one of first and second routing mode flags and a first route to a destination node in response to a connection request, and establishes a connection to a first intermediate node located along the first route. The first intermediate node is responsive to the first flag for extending the connection along the first route if there is an acceptable link in the first route. If there is no acceptable link, it finds a first route section therefrom to the destination node and extends the connection along the first route section if a total cost of links from the source node to the destination node using the first route section is less than a cost threshold, or cranks the connection back to an upstream node if there is none of such route sections.

Abstract: The data processors of the present invention transfer the contents of address registers and program registers through an unused bus during the cycle of writing into registers and execute, in one cycle, a load instruction or a store instruction that requires address calculation, although the processors have two buses and one arithmetic/logic unit. Also, the data processors assign basic arithmetic instructions between registers and load/store instructions instruction codes having a basic instruction word length of one byte by functionally dividing general purpose-registers into four address registers and four data registers.

Abstract: The present invention provides a method of processing transaction requests from client applications within a computer network having a plurality of client servers. Each client server has a work share and a set of attributes that including a name, an address and a list of services for fulfilling transaction requests. Each transaction request identifies attributes necessary for fulfilling the request. The method entails identifying a set of client servers having the necessary attributes and defining a work distribution function. The work distribution function, which distributes transaction requests, randomly selects a client server from the set of client servers, according to work shares of the client servers.

Abstract: A system for generating operating statistics for a network interconnecting at least two stations wherein each of those stations may send and receive messages during a session is implemented in software programmed to monitor the messages on the network, assign a direction to each of the messages with respect to the session based on the monitoring step, determine the role assumed by each of the stations based on the assigning step and calculate statistics for one of the stations based on the determining step.

Abstract: A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. For a given size K and X, K divisible by X, a triangular array containing K processor elements located on each edge of an equilateral triangular array is partitioned into K/X triangular arrays of dimension X and K(K-X)/2X.sup.2 square processor arrays of dimension X. An algorithm partitions a square array into two triangular arrays, each of dimension X.

Abstract: A state machine bus controller for interfacing the CPU of a micro-computer based system with memory and I/O device is described. The controller, while capable of interfacing with a bus which is synchronous in nature, can maintain synchronous handshake with more than one type of microprocessor while providing function and timing parameters to satisfy requirements of an asynchronous bus and more than one type of device which reside on the bus.

Abstract: In an information processing system of the present invention, a vector processor has a plurality of vector pipeline sets operable under control of an instruction controller. The vector pipeline sets are operable in a parallel mode or in an individual mode with reference to an operation mode flag kept in a mode flag register. The instruction controller includes a plurality of vector instruction control units which correspond to the respective vector pipeline sets and which monitor states of the vector instruction control units to detect whether or not an error has taken place in each of the vector instruction control units. The vector pipeline sets are connected to a vector data memory through a pipeline crossbar switch to fetch a common data signal from the vector data memory on demand.

Abstract: A data processing system provides annotation of a document with annotations inputted through an electronic tablet, a keyboard and an audio assembly. The annotations are entered in a modeless operation of the three input streams. Input by the tablet utilizes a two ended pen. One end of the pen is used for writing annotations to be added to a document and the second end of the pen is used for erasing the added written annotations. Files record the annotations made to the document in a manner which allows a time sequenced playback of the annotations including handwritten, typed and voiced annotations. A state machine of various procedures and controllers which call the procedures is used for processing the annotations as they are made, for replaying the annotations at a subsequent desired time, and for printing the annotations.

Abstract: A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.

Abstract: A microprocessor conforming to the X86 architecture is disclosed which includes a linearly addressable cache, thus allowing the cache to be quickly accessed by an external bus while allowing fast translation to a logical address for operation with functional units of microprocessor. Also disclosed is a microprocessor which includes linear tag array and a physical tag array corresponding to the linear tag array, thus allowing the contents of a microprocessor cache to be advantageously monitored from an external bus without slowing the main instruction and data access processing paths.

Abstract: When a rewriting instruction data is provided to an instruction decoder from a read only memory for a program, the instruction decoder decodes the data and provides an instruction rewriting control signal to a writing block. Thereby, the writing block receives a data following the writing instruction data from the ROM and writes the received data in the rewritable area of the instruction decoder. When an instruction data is provided to the instruction decoder from the read only memory under this condition, an instruction which is different from the instruction therefor output when there is no rewriting instruction is therefor output based on the same instruction.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: An associative memory processor architecture is disclosed for the fast and efficient execution of parsing algorithms for natural language processing and pattern recognition applications. The architecture consists of an associative memory unit for the storage of parsing state representations, a random access memory unit for the storage of the grammatical rules and other tables according to which the parsing is done, a finite state parsing control unit which embodies the chosen parsing algorithm, and a communications unit for communication with a host processor or external interface. The use of associative memory for the storage of parsing state representations allows the architecture to reduce the algorithmic time complexity of parsing algorithms both with respect to grammar size and input string length, when compared to standard software implementations on general purpose computers.

Abstract: A computer system simulator concurrently models both processor operation and signal logic behavior and provides a high degree of user interaction and flexibility in the observation and control of signal values and memory contents during the execution of a simulation. During simulation, source equations for signals can be requested for display either through direct input of a signal name or through graphical interface with the simulation display. Signal equations can in this manner be traced back through several levels, which conveniently provides important information during the observation and modification of signal values. Memory areas may be associated with a processor and loaded with data to be executed by that processor during the simulation. The data can be displayed in both numerical and assembly code mnemonic form, and may also be modified by entering numbers or assembly instructions. The simulated processor execution may thus be interactively modified during the simulation.

Abstract: An FSM data structure is encoded by generating a transition unit of data corresponding to each transition which leads ultimately to a final state of the FSM. Information about the states is included in the transition units, so that the encoded data structure can be written without state units of data. The incoming transition units to a final state each contain an indication of finality. The incoming transition units to a state which has no outgoing transition units each contain a branch ending indication. The outgoing transition units of each state are ordered into a comparison sequence for comparison with a received element, and all but the last outgoing transition unit contain an alternative indication of a subsequent alternative outgoing transition.

Abstract: The invention provides a novel data processor containing specific instructions including that which invalidates the content or branch records stored in cache memory, instruction queue, instruction pipeline, and branch prediction mechanism, and that which fetches and executed instructions having propriety, so that the data processor to securely coordinate the instruction string of main memory and those instructions to be actually processed, thus eventually preventing the instruction pipelines from conflict between them.

Abstract: An apparatus (100) utilizes a shift register (107) to select which of multiple synthesizers (115, 117) is to receive programming information. This allows multiple synthesizers (115, 117) to be programmed based on input from a single programing line group (102). The number of devices that can be programmed is limited by the number of parallel outputs available from the shift register (107).

Abstract: To analyze a physical phenomenon by a computer having a plurality of vector processors and a parallel computer, there is generated submatrices in a preconditioning for obtaining solutions of simultaneous linear equations. Nonzero elements of the coefficient matrix are stored with column number indices assigned thereto such that the elements of the coefficient matrix and the data of right-side vector are scaled according to a sum of absolute values of nondiagonal elements of the coefficient matrix and a diagonal element related thereto. The nonzero elements are sorted depending on magnitude of their absolute values to subdivide the nondiagonal nonzero elements into m submatrices E1, E2, . . . , Em each having substantially a comparable order.

Abstract: A method for minimizing advertising of metrics in a network. The described invention minimizes advertising of metrics by providing for each node to identify to the other nodes the metrics it will utilize in path selection. Each node then advertises only those metrics which are utilized by at least one other node in the network.

Abstract: The present invention comprises a computer system having a plurality of processors configured in an architecture having at least two subgraphs wherein at least a first subgraph and a second subgraph having the same topology and corresponding processors being stepwise complimentary for a data redistribution operation. Each processor of the computer system comprises a plurality of data-blocks and an executable program. The executable program performs the data redistribution operation by first exchanging in parallel the first half of the data-blocks of a processor in the first subgraph with the corresponding processor of the second subgraph. The redistributions of data with the corresponding stepwise complimentary processors are then simultaneously performed utilizing the full bandwidth of the data links. A reverse exchange of the first half of the data blocks between the processors of the first and the second subgraphs are then performed at the end.