Abstract: In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.

Abstract: In order to measure coverage of branching passes in a microprogram executed in a logic simulator, a first and a second memories are connected to a simulation executor. The first and the second memories hold, as a current and a latest step numbers, numbers of two instruction steps in the microprogram which are currently and latest executed by the simulation executor, respectively. When a pair of the current and the latest step number is coincident with one of the branching passes held in a branch table for holding information representative of each of the branching instruction steps and a coverage table for writing a passing time number for each of the branching passes, the passing time number is renewed. The coverage is computed from the passing time numbers written in the coverage table after the simulation is completed.

Abstract: A post-processing is executed on a mantissa M and an exponent E of a floating point binary number as a result of subtraction for example, thereby to obtain a mantissa m and an exponent e of the result of the post-processing. Therefore, an output (E-1) of a decrementer and an output (amount of cancelling of mantissa LSA) of an advancing 1 detecting circuit are entered into a minimum value selecting circuit. The minimum value selecting circuit is adapted to set a shift amount SH to (E-1) and a magnitude-relation judging signal CR to 1 when (E-1) is smaller than LSA (that is, when a denormalize processing is required). When (E-1) is not smaller than LSA (that is, when a normalize processing is required), SH is set to LSA and CR is set to 0. A left shifter is adapted to supply, as the mantissa m of the result, a value obtained by executing a left shift processing having a shift amount SH on the mantissa M.

Abstract: Two new classes of interconnection networks are described. The new classes of interconnection networks are referred to herein as the hierarchical shuffle-exchange (HSE) and hierarchical de Bruijn (HdB) networks. The new HSE and HdB networks are highly regular and scalable and are thus well suited to VSLI implementation. In addition, they can be adjusted to match any set of packaging constraints. These new networks are also efficient in supporting the execution of a wide range of algorithms on computers whose processors are interconnected via one of the networks fabricated in accordance with the teachings of the invention. Such computers, also contemplated by the invention, are referred to herein as HSE and HbB computers. Furthermore, methods for implementing the aforementioned wide range of algorithms, particularly those in the classes of Ascend and Descend algorithms, on the novel HSE and HdB computers, constitute a further aspect of the invention.

Abstract: An apparatus for interfacing between a plurality of application programs and at least one display adapter having functions for supporting a display, the apparatus including first driver apparatus providing an interface from a first one of the application programs to functions of a display adapter, second driver apparatus providing an interface from a second one of the application programs to functions of the display adapter, and access apparatus, coupled to both driver apparatus and to the display adapter, for providing both driver apparatus common access to selected functions of said display adapter.

Abstract: An associative memory processor architecture is disclosed for the fast and efficient execution of parsing algorithms for natural language processing and pattern recognition applications. The architecture consists of an associative memory unit for the storage of parsing state representations, a random access memory unit for the storage of the grammatical rules and other tables according to which the parsing is done, a finite state parsing control unit which embodies the chosen parsing algorithm, and a communications unit for communication with a host processor or external interface. The use of associative memory for the storage of parsing state representations allows the architecture to reduce the algorithmic time complexity of parsing algorithms both with respect to grammar size and input string length, when compared to standard software implementations on general purpose computers.

Abstract: A priority encoder-includes an encoder for coding an input consisting of a plurality of bits, selectors, respectively provided for bit input terminals of the encoder, for respectively receiving corresponding ones of a plurality of bits of an operand input, each of the selectors including a switch circuit to be controlled by an operand input bit, a carry line connected in series with the switch circuit and connected in series with all of the selectors, a first precharge circuit, connected to a carry line portion on one end side of the switch circuit, for precharging the carry line at a predetermined timing, a first detector which is controlled by an enable signal for designating upper bit priority and detects whether a potential of a carry line portion on an upper bit side of the switch circuit is at a discharge level, a second detector which is controlled by an enable signal for designating lower bit priority and detects whether a carry line portion on a lower bit side of the switch circuit is at a discharge

Abstract: A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

Abstract: A system and method for allowing communications sessions to be established between two or more computer processors and a remote terminal in a communications network where only one host to terminal session may be created. The system allows processors in a loosely coupled processor complex to determine whether another of the processors has an existing communications session with the requested remote device. If so, any new request for a communications session with that remote device will be routed through the processor with the established link. The interprocessor routing uses service transaction programs within each of the processors in a loosely coupled complex to establish the required communications sessions and to serve as an intermediary for passing messages between the requesting host and the remote device.

Abstract: A chordic keyboard system for communicating with a data processing system. The chordic keyboard system includes ergonomic features, i.e., a keyboard that is tilted and an integrated palm rest. The chordic keyboard system also includes data entry features, i.e., storage for data representative of a plurality of chords, each chord corresponding to a subset of the plurality of keys of the chordic keyboard, and for a plurality of symbols, each data representative of a chord represented by and corresponding to one of the plurality of symbols according to a frequency-of-use index of the symbol and further according to a correlation based on a chord-difficulty index of the chord. The plurality of groups includes an alphabetic group, a punctuation/cursor control group, an editing/control function group, a numerical/mathematical group, and a punctuation/symbolic-type group.

Abstract: For use in a propulsion control system, a microprocessor based central processing unit board includes both Multibus I and Multibus II interfaces. Multibus I master interface and Multibus slave interface controllers are designed for high data throughput by using programmed logic design (PLD) technology. In addition, the need for latching of data transceivers used in conventional Multibus I designs is eliminated. The Multibus II interface is removable.

Abstract: Disclosed is a current driver that includes an array of current buffers and a program control circuit. The program control circuit responds to an externally generated programming signal to generate buffer direction control, daisy chain configuration control, and tristate control signals. The buffers of the array of current buffers are individually programmed by the direction control and the daisy chain configuration control signals to transmit data in one of a forward and reverse direction and to daisy chain a buffer to a preceding buffer, respectively. The array of current buffers is responsive to the tristate control signal to operate in a tristate mode. The array of current buffers may be reprogrammed in response to a reset signal.

Abstract: An extended mode analyzer (EMA) processes source code modules, detects suspicious instruction patterns and produces recommendations for code modification. The EMA applies knowledge based technology to the problem of massive source code conversion. The knowledge base component within the EMA models any given source code module using a hierarchical class/attribute structure. All source lines occurring in a given module are partitioned into homogenous classes characterized by function or instruction type. Higher level programming concepts are abstracted from lower level implementation details by drawing correspondences between class members which constitute instruction sequences related by common elements. When inferencing begins, the existence of class members meeting certain criteria trigger events which change the state of the world as seen by the knowledge base, in turn triggering other state changing events and so on until a state of equilibrium is achieved.

Abstract: In an apparatus for controlling a signal processing system to operate in high and low speed modes, a control unit determines a speed of system clock signals in accordance with the interpretation of a program when external clock signals are received. When a speed of the system clock signals is determined, the control unit controls the production of the system clock signals of a frequency dependent on the speed. As a result, a peripheral circuit of a low speed can be controlled to operate without the necessity of a complicated interface circuit, and a system of a high speed such as a system for the so-called television game can also be controlled to operate. Further, a limitation on an operation speed of a peripheral circuit is excluded so that an expansion of a signal processing system can be easy to be performed. Still further, all circuits of the signal processing system can be under operation states because a low speed mode is first realized when a power supply is turned on.

Abstract: A high speed bus for communicating between a processing component and a display component of a computer. The high speed bus substantially enhances video graphics application performance by allowing the process component and the display component to communicate without using the system bus. By coupling the processing component and the display component via a high speed bus, video graphics instructions may be routed directly from the processing component to the display component, thereby eliminating the delay associated with the slower standard system bus lines. By using the high speed bus, the processing component is able to communicate with the display component without having to place instructions onto the busier system bus.

Abstract: A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

Abstract: A network for parallel processing for high performance parallel processing systems. Such a network solves the network communication problem by making use, in its nodes, of large size memory units capable of being simultaneously accessed by several processing units installed on the network edges intersecting that node. The processing units provide a large number of high performance virtual processors performing processing operations on both the two memories between which the processing unit is connected and transfer operations therebetween.

Abstract: A computer installation is programmed for storing data in a magnetic disk DASD (direct access storage device) in the form of a track number identified by DASD cylinder number (CC) and DASD head number (HH). A re-writable, multi-disk optical storage which stores information in a fixed-block architecture including a sequence of sectors having the form of spirals on optical disk surfaces is enabled to emulate magnetic DASD by calculation-based conversion of storage references to magnetic DASD tracks to fixed-block optical sectors.

Abstract: A SIMD parallel processor includes two types of circuitry interconnecting its processing units: One kind interconnects the processing units into an array so that each processing unit can transfer data to an adjacent processing unit in the array and can receive data from an adjacent processing unit; the processing units can, for example, be interconnected in a one-dimensional array. Another kind of interconnecting circuitry includes bus circuitry to permit greater freedom in transferring data to and from processing units. Connected to the bus is a register, so that data can be transferred between processing units by first transferring data from one processing unit to the register and by then transferring data from the register to another processing unit. Or data stored in the register can be sent to a subset or to all of the processing units. Similarly, control circuitry can itself provide data on the bus for transfer to one, a subset, or all of the processing units.

Abstract: An FSM data structure is encoded by generating a transition unit of data corresponding to each transition which leads ultimately to a final state of the FSM. Information about the states is included in the transition units, so that the encoded data structure can be written without state units of data. The incoming transition units to a final state each contain an indication of finality. The incoming transition units to a state which has no outgoing transition units each contain a branch ending indication. The outgoing transition units of each state are ordered into a comparison sequence for comparison with a received element, and all but the last outgoing transition unit contain an alternative indication of a subsequent alternative outgoing transition.