Abstract: A multi-master digital computer system has a bus, a plurality of master devices connected to the bus, a plurality of slave devices connected to the bus, and a bus controller for arbitrating bus requests by the master devices and for granting the bus to a selected one of the plurality of the master devices. Each master device is capable of originating a bus cycle to transmit data to or receive data from a desired slave device. The bus controller grants the bus to a selected master device which enters an address master state and addresses the desired slave device. The selected master device is transferred to a bus master state where a data transfer to or from the slave device is initiated. The selected master device then transfers to a data master state unless the selected master device wants, and is permitted through an arbiter, to retain control of the bus. The bus controller grants a bus request to a requesting master device through to the arbiter.

Abstract: Disclosed is a masking technique for a SIMD processor (10) which is capable of masking a plurality of individual machine operations within a single instruction incorporating a plurality of operations. To accomplish this each different machine operation within the instruction includes a number of masking bits which address a specific location in a mask register (60). The mask register (60) includes a mask bit bank (62). The mask location selected within the mask register (60) is bit-wise ANDed with a mask context bit (66) in order to establish whether the processing element will be enabled or disabled for a particular conditional sub-routine which is called. One of the bit locations in the mask bit bank (60) is a hard-wired unconditional bit which overrides the mask context bit (66) in order to enable the processing elements in special situations. In addition, a scalar mask bit is provided to facilitate scalar processing.

Abstract: A control device for an image forming apparatus with plural loads includes plural execution units for executing plural processes in accordance with at least one of a plurality of programs stored in the program memory, a monitor unit for controlling an image forming sequence and monitoring process operations of plural control execution units in accordance with at least one plurality of programs, an input unit for inputting data required for the operations of the plural control execution units, a system bus to which the system execution units in the monitor access, and a memory unit, contents of which can be read out and written in by the plural execution units and monitor unit, wherein the monitor unit and the plural control execution unit access a system bus in a time-divisional manner such that the monitor unit and the plural control execution unit is prepared to be operated in turn, and the monitor unit selects fewer of the execution units when a task to be allocated requires faster processing and wherein t

Abstract: A point to point communication apparatus, such as a digital radiopager (RP), having a non-volatile electrically programmable store which stores a radio identification code (RIC) or apparatus configuration information. The store can be programmed/reprogrammed by sending coded light signals to a light sensor. The coded programming/reprogramming light signals are supplied from an external source, such as a personal computer, and conform to a protocol which on being recognized causes a controller to permit access to the programmable store. The light sensor may also be used to sense the ambient light and control energization of a back light of a LCD panel.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A multi-stage circuit switched network for improving connection establishment using intelligent switching devices. As a transmission makes its way through the network stages, the probability of connecting to a destination increases, i.e., the chance of encountering a blocked device output is decreased. This is opposite of most traditional networks, whose probability for success diminishes with every stage in the connection sequence.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized. functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A mini-cache module is added to a computer system to increase throughput or may also be added to enhance the functionality of a general cache memory unit. The mini-cache module refills and stores frequently used data words concurrently during processor operations and provides them to the processor, eliminating the need to access a system bus to main memory. A data queue storage stores a data block of words from main memory and makes them available to requests from the main processor (if the requested address matches an address register block in the mini-cache). If an address "hit" occurs, then the mini-cache will prevent any system bus request to main memory and additionally will monitor the system bus for any "Write" operations which might feasibly change the validity of data in the data storage block of the mini-cache. In this case the data stored in the mini-cache is invalidated and cannot be used by the processor.

Abstract: A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.

Abstract: A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each configuration file for programming an algorithm to be executed by the matrix array, an input/output bus for supplying data to the matrix array for processing and for obtaining processed data from the matrix array, a memory device for storing data, a VPM controller for controlling the overall operation of the virtual processor including providing operation sequence maps, providing parameters for specific operations, and providing status information, a data bus controller for controlling the data flow to the matrix array for processing, and a configuration controller for controlling the sequence of reconfiguration of the matrix array to process data by a specific sequence of algorithms.

Abstract: A computer installation is programmed for storing data in a magnetic disk DASD (direct access storage device) in the form of a track number identified by DASD cylinder number (CC) and DASD head number (HH). A re-writable, multi-disk optical storage which stores information in a fixed-block architecture including a sequence of sectors having the form of spirals on optical disk surfaces is enabled to emulate magnetic DASD by calculation-based conversion of storage references to magnetic DASD tracks to fixed-block optical sectors.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A recognizing and judging apparatus for a learning and recognizing processing to be effectively performed in a short period of time, the apparatus including a plurality of recognition units in a multi-layered hierarchical network structure with one or more path output terminals of the recognition units of an upper layer being connected with one or more path input terminals of the recognition units of a lower layer.

Abstract: A sequencer for use in a pipeline architecture includes circuitry for determining whether the previous instruction was a conditional jump instruction and whether the condition was met, circuitry for determining whether the current instruction is a conditional jump, and circuitry inhibiting a branch responsive to the current instruction, if the previous instruction was a conditional jump and the condition was met. Additionally, circuitry may be provided for treating a CALL instruction as a one-cycle unconditional jump if the preceding instruction was a conditional jump and the condition was not met, thereby implementing a two-cycle IF-THEN-ELSE instruction.

Abstract: A method for testing the timing parameters of a system design is presented, especially suited for use in testing for timing violations between the pins of a semiconductor device. A description of the timing constraints of the various modules of a design is written in a common non-technical vernacular, and functions as an input file. A Timing Shell Generator converts the input file description into a simulator-environment-compatible output code-language file description. The output code-language file is operative to implement the timing constraints of the original input file during simulation such that any violations of the prescribed timing constraints are indicated to the tester who can then take appropriate action.

Abstract: A computer programming system provides animated program sources that are created in an interactive visual manner. Animation is integrated with computer programming to allow a user or programmer to visualize programming flow and operation. Animated depictions are thus produced for dynamic phenomenon, such as concurrent computations. The program system supports a computation model of concurrent communicating agents. A concrete metaphor for the computation model is provided, e.g. agents are implemented as buildings; rules or methods are implemented robots or workers inside of buildings; local state is posted on bulletin boards inside of buildings; couriers carry messages between buildings; and so on.

Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: A system and method for allowing events in a rich object-oriented environment to be monitored by functional processes within that environment. Events can be monitored by any number of functional processes, and the monitoring functional processes can take action based upon the monitored event received. Multiple object-oriented environments are provided with each environment comprising a distributed communications manager. These distributed communications managers facilitate the monitoring of events by the functional processes. An overall communications manager is also provided to monitor the entire system.