Abstract: In a system including a control processor, a coprocessor, a program memory and a data memory, the control processor accessing the program memory during an instruction fetch cycle and the data memory during an instruction execution cycle, an apparatus for controlling access to the data memory has a control processor interface for coupling to the control processor, a coprocessor interface for coupling to the coprocessor, and instruction fetch detection logic, coupled to the control processor interface, for detecting when the control processor requests access to the program memory and generating, in response, a first access control signal. The apparatus also has scheduling logic, coupled to the coprocessor interface, for detecting when the coprocessor requests access to the data memory and, in response, generating a second access control signal. A switch in the apparatus couples memory address, memory data and memory control signals to the data memory alternatively from the control processor or the coprocessor.

Abstract: A bus interface system has a bus interface, a common memory, a local bus, and a memory controller for use in a memory control. The memory controller has a buffer and is connected to the local bus. The bus interface has a burst disassembling control circuit which disassembles burst transfer data into one or a plurality of block transfers and one or a plurality of one-word transfers, which are supplied to the memory controller so that when the bus interface receives all requested data received from the common memory during a read access, the bus interface adds information on a destination device, connected to a system bus, to all the requested data and sends all the requested data with that information to the destination device via the system bus.

Abstract: A multiprocessor system includes a plurality of processors each of which selects one resource from a plurality of executable resources and processes the selected resource. A memory stores priority levels of the executable resources for each of the processors. A resource selector selects a resource to be processed by each of the processors from among the executable resources, on the basis of the priority levels stored in the memory. A resource is selected based on a highest priority level corresponding from among the executable resources. Executable resources are processes or pages of a memory.

Abstract: Disclosed is a pipeline information processing circuit which comprises a register control unit for outputting a plurality of data held in registers at a time; an arithmetic operation unit for carrying out a collective arithmetic operation of a plurality of data; and a bypass control unit for comparing an operation result outputted from the arithmetic operation unit and a data outputted from the register control unit, selecting a data to be an object of the next arithmetic operation, and transferring the selected data to the arithmetic operation unit through a suitable bypass.

Abstract: An extra large number-of-input complex logic circuit, employed inside a microprocessor for performing a large number of controls and arithmetic operations, is constructed utilizing N(N.gtoreq.2) number of a unit logic circuit each comprising M(M.gtoreq.1) input CMOS logic circuits and one bipolar transistor, whereby respective outputs are integrated to produce one output in response to M.times.N number input signals to provide a high speed, high density integration and low power consumption microprocessor.

Abstract: A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.

Abstract: A computer-based apparatus and method for gathering Information for data model and Process model development includes a plurality of terminals on a local area network at which multiple users enter Information in a structured manner in response to an ordered sequence of screens displayed for a given project; a centralized database for receiving the Information from the multiple users; and a bridge program for transforming the group-entered Information stored in the database into a format that a computer-based information engineering tool can create into a model. An analyst workstation is included to enable only an analyst to edit gathered Information in response to comments from users and provide certain consensus inputs.

Abstract: An FSM data structure is encoded by generating a transition unit of data corresponding to each transition which leads ultimately to a final state of the FSM. Information about the states is included in the transition units, so that the encoded data structure can be written without state units of data. The incoming transition units to a final state each contain an indication of finality. The incoming transition units to a state which has no outgoing transition units each contain a branch ending indication. The outgoing transition units of each state are ordered into a comparison sequence for comparison with a received element, and all but the last outgoing transition unit contain an alternative indication of a subsequent alternative outgoing transition.

Abstract: An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a host and a guest ALB identifier (ALBID) and a host and a guest ALBID validity indicator. Control State Software generates and stores the host and guest ALBIDs in the host and guest ALBID registers and marks valid the host and guest ALBID validity indicator whenever a host or guest mode is initiated or a logical purge is requested by a logical processor and for storing the host or guest ALBID stored in the host and guest ALBID registers when an ALB entry is made in the ALB by a logical processor.

Abstract: Personal computers, a first processor and a second processor belonging to a processor circuit such as a PC card, communicate with one another via a quasi dual-port RAM. The first processor and the second processor alternately read data out of the RAM and write other data into the RAM. Furthermore, the second processor communicates directly with an associated peripheral device. By offering the possibility of, in a first mode, communication between the first processor and the RAM, and communication among the second processor, the peripheral device and the RAM and, in a second mode, communication between the first processor and the peripheral device without using the RAM and without the intervention of the second processor, the PC card becomes sufficient for test purposes and permits backup possibilities. By storing a synchronization protocol into the first processor and into the second processor, the first processor and the second processor can be easily synchronized with each other.

Abstract: A serial data transfer apparatus includes a time base counter that counts by a clock signal (CLK). The count value of the time base counter at the point of time when the reception of the serial data (R.times.D) is completed is written into the reception buffer together with the reception data. Accordingly, in the central processing unit, when the reception data (R.times.D) is to be processed, the time difference since the reception serial data (R.times.D) can be detected by reading out the count value of the time base counter written in the reception buffer and by reading out the count value of the time base counter at present from the time base counter. Accordingly, time management of the reception data can be performed.

Abstract: This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Abstract: A method and structure for logically disconnecting an on-chip virtual-to-physical address translation unit from a microprocessor by holding the dynamic circuits of the translation unit in precharged state. In one embodiment, the method and structure provide a fixed remapping for the virtual address. A powering down of the translation unit effects power savings when the translation unit is not required.

Abstract: An FSM data structure is encoded by generating a transition unit of data corresponding to each transition which leads ultimately to a final state of the FSM. Information about the states is included in the transition units, so that the encoded data structure can be written without state units of data. The incoming transition units to a final state each contain an indication of finality. The incoming transition units to a state which has no outgoing transition units each contain a branch ending indication. The outgoing transition units of each state are ordered into a comparison sequence for comparison with a received element, and all but the last outgoing transition unit contain an alternative indication of a subsequent alternative outgoing transition.

Abstract: Processor circuit having two communication paths suitable for modem applications is described. The card includes a receiving/transmitting (R/T) circuit and a first processor. The R/T circuit is coupled to a second processor, e.g., the processor of a personal computer. It is also coupled to a network via the first processor. Data to and from the network is routed by the first processor to the second processor via the R/T circuit. A dual access memory device is also used to couple the first and second processors together. Use of the dual access memory device simplifies error diagnosis and the passing of error information between the first and second processors. A new main program is placed in a RAM of the first processor without the need for an expensive emulator or use of an EEPROM through the use of the dual access memory device. By storing an auxiliary program, e.g.

Abstract: An improved data processor includes a high-speed memory that functions as a data cache during normal operation and as a trace memory to debug software in an in-circuit emulation mode. A register counts the number of storage location and overflows when a predetermined number is exceeded to cause an exception which transfers information off-chip from the trace memory. In one embodiment a starting address is stored and compared to a program counter of an instruction completely executed in the execution unit to begin the tracing.

Abstract: A data structure for use in hyphenation is created by including hyphen codes at the acceptable hyphenation points of words and then collapsing the words into a minimal state determinized FSM data structure. The transitions of the data structure are sorted so that a hyphen code that has alternatives is positioned before its alternatives. The data structure is then encoded for compactness. In searching with a word, if a mismatch occurs in the branch of the data structure that depends from a hyphen code, the search continues with its alternatives, because a match could be found in a branch depending from one of the alternatives. The data structure may be accessed with a hyphenated word to check hyphenation or spelling. It may be accessed with an unhyphenated word to retrieve its hyphenation points. It may be accessed with a number corresponding to a word to retrieve that word with its hyphenation points.

Abstract: A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages with data values to start new threads of computation. Each node also includes a synchronization coprocessor for processing start messages from the same and other nodes of the system. The coprocessor processes the messages from a message queue to store values as operands for threads of computation, to determine when all operands required for a thread of computation have been received and to provide in a continuation queue an indication to the data processor that a thread of computation may be initiated. The data processor subsequently nonsynchronously initiates the thread of computation. Alternatively, a single processor may perform the continuation and message processing functions in an interleaved sequence.

Abstract: A system for managing an assemblage of entities. The entities interface within the assemblage for control of primary information handling functions and further interface with the system to permit the carrying out of management functions. The system includes management modules adapted to carry out management functions by independently interpreting and executing commands, a kernel including a table of dispatch pointers for directing the commands to the respective modules in which they are to be interpreted and executed, and an enroller for enrolling new modules into the system by adding further pointers to the table.

Abstract: The ADL system provides a way in which computer programs written in different programming languages can share data. The ADL system comprises the ADL language and the facilities necessary to perform the data sharing function. The ADL language uses the concept of a data description and conversion module. A data description and conversion module, or more simply, an ADL module is composed of declarations and plans. Each declaration is an ADL description of how a particular program environment represents data. The plan portion of the ADL module contains ADL statements that instruct the computer system to convert the data representations of the source program environment into the data representations of the target program environment.