Abstract: A method of forming a FET with an having a self-aligned pocket implant, comprising the following steps. A substrate is formed having a substrate dielectric layer thereon and a first oxide layer over the substrate dielectric layer. The first oxide layer having an upper surface. A trench is formed through the oxide layer, the substrate dielectric layer, and partially through the substrate. The trench having a bottom and side walls. A second oxide layer is formed along the bottom and said side walls of said trench within the substrate. A dopant is selectively ion implanted into the substrate is achieved to form lightly doped layers adjacent the side walls of the trench within the substrate. A self-aligned channel implant and a pocket implant are ion implanted at predetermined respective depths in the substrate below the trench bottom is achieved. Side-wall spacers on the side walls of the trench are then formed with the side-wall spacers each having a top surface below the upper surface of the first oxide layer.

Abstract: Aspects for deprocessing of a flip-chip, multi-layer integrated circuit from the backside are described. In an exemplary method aspect, the method includes reducing a first backside layer of the multi-layer integrated circuit to a predetermined thickness, and exposing an active region of the multi-layer integrated circuit to allow device analysis of the multi-layer integrated circuit. The method further includes removing a metal layer beneath the active region to expose interlayer dielectric material, performing a bulk delayering of the interlayer dielectric material to expose a next metal layer, and continuing to delayer the multi-layer integrated circuit layer-by-layer from the backside for analysis of the multi-layer integrated circuit.

Abstract: The present invention provides a method for fabricating a submicron metal-oxide semiconductor field-effect transistor (MOSFET). The method includes providing a gate on a substrate, the substrate having a source side and a drain side, the drain side having a spacer area; forming a spacer at the spacer area; performing a halo implant at the source side and the drain side, wherein the spacer prevents implantation in the spacer area, where the spacer facilitates formation of a lateral asymmetric channel; forming heavily doped extensions in the source side and the drain side, where the spacer prevents doping in the spacer area; removing the spacer; and forming a lightly doped extension in the drain side, where the heavily doped extensions and the lightly doped extension prevent hot carrier injection.

Abstract: A capacitor for high density DRAM applications comprises a high-.di-elect cons. capacitor dielectric such as BST or PZT in an arrangement which obviates the need for barrier layers during fabrication. The fabrication process allows for electrode placement by simple sputter deposition and further provides for the possibility of capacitor spacing below that of conventional lithographic techniques.

Abstract: The present invention proposes a method for fabricating a non-volatile memory device using nano-crystals with an increased etching rate and an increased oxidation rate at the grain boundary, which is used in high-speed and low power consumption device. The method for fabricating a non-volatile memory device using nano-crystal dots comprises following processes. First process is to fabricate a tunneling dielectric 204 and a thin amorphous silicon continuous film. Second process is to fabricate a poly-silicon layer by poly-crystallizing the amorphous silicon film. Third process is to fabricate nano-crystals 212 by etching the poly-silicon layer. Fourth process is to fabricate an interlayer dielectric 214 on the nano-crystals 212. Fifth process is to attach a poly-silicon film to the interlayer dielectric 214 and fabricate a gate 216 and interconnects 220.

Abstract: A method of manufacturing a semiconductor wafer wherein each layer to be scanned is scanned in a scan tool after determination of whether the current recipe is contained in the scan tool. The recipe in the scan tool is compared to the current recipe stored in a server. If the recipe in the scan tool is not the current recipe the current recipe is loaded into the scan tool from the server. The recipes in the server are updated from associated scan tools.

Abstract: The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. In one aspect, the invention includes, a semiconductor processing method comprising: a) forming an organic layer over a semiconductive substrate; and b) implanting a conductivity-enhancing dopant through the organic layer and into the semiconductive substrate. In another aspect, the invention includes a semiconductor processing method comprising: a) providing a semiconductive substrate and defining source and drain locations within so the semiconductive substrate; b) forming an organic layer over the source and drain locations; c) implanting a conductivity-enhancing dopant through the organic layer and into the source and drain locations to form source and drain implant regions within the source and drain locations, respectively; and d) forming a transistor gate proximate the source and drain implant regions.

Abstract: The present invention provides a method of forming a contact hole in a semiconductor wafer. The semiconductor wafer comprises a silicon substrate, a silicon--oxygen layer positioned on the silicon substrate, and a photoresist layer positioned on the silicon--oxygen layer. An anisotropic dry-etching process is performed to vertically remove the silicon--oxygen layer below the opening to a predetermined depth to form the contact hole which contains a polymer layer on its surface. A soft-etching process is performed to remove the polymer layer in the contact hole. The dry-etching process and soft-etching process are performed alternatively to vertically remove the silicon--oxygen layer under the contact hole until the surface of the silicon substrate can be reached through the contact hole.

Abstract: A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH.sub.4) is deposited over the surface of the wafer using a chemical vapor deposition (CVD) tool. The deposition of silane is done at 400.degree. C. The temperature is raised in the CVD tool to a temperature in the range of 550.degree. C. to 650.degree. C. and held for 30-60 minutes. This temperature does not affect the thin film of silicon which is formed from the silane, yet provides the necessary thermal cycle to "repair" the crucial first 200 .ANG. to 600 .ANG. of the silicon surface. Normal processing steps, including a rapid thermal anneal for 30 seconds at 1025.degree. C. follow. The RTA is necessary to activate the dopants (arsenic and boron) in the source and drain of the respective devices.

Abstract: A method for forming a gate structure on a semiconductor substrate includes the following steps. A layer of a gate material is formed on the semiconductor substrate, and a patterned mask layer is formed on the layer of the gate material opposite the substrate. The layer of the gate material is then etched with an etching gas including a mixture of chlorine gas (Cl.sub.2), oxygen gas (O.sub.2), and a gas including fluorine (F) using the patterned mask layer as an etching mask. In particular, the step of forming the layer of the gate material can include the steps of forming a polysilicon layer on a surface of the semiconductor substrate, and forming a silicide layer on the polysilicon layer opposite the substrate.

Abstract: A multistage etching process is provided for etching through portions of a layer stack during the formation of a control gate in a semiconductor device. The multistage etching process allows for controlled removal of a tungsten silicide layer within the layer stack by reducing the potential for loading, microloading, over-etching, under-etching, etc. In a first stage of the multistage etching process, part of the tungsten silicide layer is selectively etched away using a plasma that exhibits an etching selectivity (ratio of tungsten silicide etch rate to polysilicon etch rate) less than about 1.2. During the second stage of the multistage etching process, the remaining amount and/or residue parts of the tungsten silicide layer is selectively etched away using a plasma that exhibits an etching selectivity (ratio of tungsten silicide etch rate to polysilicon etch rate) greater than about 1.2.

Abstract: A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer.

Abstract: The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.

Abstract: In manufacturing a transistor, a doping mask is formed above a substrate. The doping mask is constructed, so that a first region of the substrate for serving as a source in the transistor and a second region of the substrate for serving as a drain in the transistor are substantially shielded. Once the doping mask is formed, ions are introduced into a region in the substrate that is to underlie the transistor's gate structure. The ions are introduced to establish the characteristics of the transistor, such as the transistor's threshold voltage and punch-through breakdown voltage. After the ions are introduced, a gate oxide is formed to overlie a portion of the substrate. The gate structure for the transistor is then formed to substantially overlie the region of the substrate in which the ions have been introduced. Once a gate is formed for the gate structure, a source and drain are formed in the substrate.

Abstract: A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

Abstract: A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface.

Abstract: An electrode material layer of a WSi.sub.2 /polysilicon lamination layer and a conductive material layer for antireflection made of TiN or TiON and containing the direction <200> are sequentially deposited on a gate insulating film. The conductive material layer is patterned through dry etching using a resist layer as a mask to leave a portion of the conductive material layer. The resist layer may be as thin as capable of patterning the conductive material layer. After the resist layer is removed, the electrode material layer is patterned through dry etching using the conductive material layer as a mask to leave a portion of the electrode material layer. A lamination of the left electrode material layer and conductive material layer is used as a gate electrode layer. A lamination of the resist layer and conductive material layer may be used as a mask.

Abstract: A first gate oxide film is formed on a surface of a silicon substrate. A first polycrystalline silicon film is formed on the first gate oxide film, and patterned so that its side surface is tapered. Silicon oxide film exposed through the first polycrystalline silicon is removed, and a second silicon oxide film having film thickness different from that of the first silicon oxide film is formed by thermal oxidation. Thus, dual gate oxide is manufactured. Accordingly, a method of manufacturing a semiconductor device is provided which can improve reliability of the transistor and can improve production yield, by suppressing generation of foreign matters.

Abstract: Disclosed is a manufacturing method of a semiconductor device which comprises which comprises an element isolation region formation step; a side wall formation step; a diffusion layer formation step; an activation step; a silicide formation step; and a removing step. The element isolation region formation step is the one for forming a field oxide film on a semiconductor substrate to form an element isolation region. In order to form a diffusion layer by introducing impurities into the semiconductor substrate, after injecting the fluorides (ion injection species) of elements into the semiconductor substrate, a thermal treatment is performed at a lower temperature than that of a thermal treatment for activating the diffusion layer prior to the activation of the diffusion layer, and fluorine produced from the ion injection species is discharged to the outside.