Abstract: A semiconductor device and a method of making the device with a raised source/drain has a semiconductive material that is non-selectively deposited in a layer over the device area. The semiconductive material is then etched to form spacers that will form the raised soure/drain areas following doping of the spacers. The gate of the semiconductor device is protected during the etching by an etch stop layer that is grown or deposited over the structure to be protected, e.g., the gate, prior to the deposition of the semiconductive material layer. Lightly doped drain ion implantation is performed prior to the formation of the spacers, and source-drain ion implantation is performed preferably after the formation of the spacers, to create the shallow junctions.

Abstract: A semiconductor device and a method of fabricating such a semiconductor device in which a silicon nitride film constituting a protective film for ion implantation is used for improving the device structure in order that conversion of a metal film into a silicide for reducing the resistance of a shallow-junction diffused layer may not be prevented by the knock-on phenomenon of oxygen, thereby reduce the fabrication cost. A silicon nitride film, which is used as a protective film for ion implantation into a substrate and a gate polysilicon, is processed into side walls of the gate polysilicon thereby to omit the step of forming side walls by a silicon oxide film. Further, in the case where boron is diffused into the gate polysilicon, boron diffusion is suppressed by nitrogen knock-on, thereby preventing boron from going through the gate oxide film.

Abstract: A method for etching polysilicon or polycide gate electrodes over thin gate oxides is described wherein the problem of pitting and trenching of the silicon beneath the gate oxide, caused by penetration of the polysilicon etchant through the gate oxide is resolved. A cause of gate oxide penetration is found to be a native oxide formed on the exposed surface of polycide or polysilicon gate layer. The native oxide is uneven and has local thin spots which are penetrated by the traditional polysilicon etchants. The erratic penetration of the native oxide produces an uneven etch front which propagates down to the gate oxide. Gate oxides thinner than about 125 .ANG. are incapable of absorbing this irregularity during polysilicon over etch and are penetrated causing deep pockets in the subjacent silicon. The novel method first etches the native oxide with a brief highly selective fluorocarbon etch and then etches through the polycide or polysilicon with C.2 and HBr to endpoint on the thin gate oxide.

Abstract: A memory cell of the EEPROM type formed on a semiconductor material substrate having a first conductivity type includes a drain region having a second conductivity type and extending at one side of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region. The region of electric continuity is produced by implantation at a predetermined angle of inclination.

Abstract: A method for manufacturing a semiconductor device having a high durability against a hot carrier problem and reliable transistor characteristics comprises the steps of forming a first silicon oxide film by atmospheric pressure CVD, forming a silicon nitride film by low pressure CVD to a thickness of 30 to 200 angstroms, and forming a silicon oxide film by biased electron cyclotron resonance CVD (ECR-CVD) using a silane gas as a source material while applying a radio frequency electric field to the substrate. The ECR-CVD silicon oxide film provides a sufficient amount of active hydrogen ions, and silicon nitride film allows movement of an adequate amount of the active hydrogen ions to thereby eliminate the hot carrier problem and recovery of transistor characteristics from the plasma damage.

Abstract: A method of manufacturing a semiconductor device having a self-aligned contact hole includes a step of forming first gate electrode structures having a high pattern density on a gate insulating film in a first area of a semiconductor substrate and second gate electrode structures having a low pattern density on the gate insulating film in a second area, a step of forming first and second insulating films having different etching characteristics over the semiconductor substrate, a step of anisotropically etching the first and second insulating films in the second area by masking the first area to form side spacers on the second gate electrode structures, a step of forming an interlayer insulating film over the semiconductor substrate, and a step of forming in a self-alignment manner an opening reaching the source/drain region in the first area, by using the second insulating film as an etching stopper. This method allows to reliably form a self-aligned contact hole even if the pattern density is high.

Abstract: This invention includes a semiconductor device having a gate formed on a semiconductor substrate with a low hydrogen content etch stop or barrier layer formed over the gate, and methods for manufacturing a semiconductor device with an etch stop or barrier layer with low free hydrogen content. The semiconductor device may have a hydrogen getter layer formed between the gate and the etch stop or barrier layer. The etch stop or barrier layer is a high temperature PECVD nitride film, a high temperature PECVD oxynitride film or a high temperature LPCVD nitride film. The hydrogen getter layer is P-doped film having a thickness between about 500 .ANG. and about 2000 .ANG. and is a PSG, BPSG, PTEOS deposited oxide film, or a BPTEOS deposited oxide film. The low free hydrogen content of the etch stop layer or barrier layer is achieved by a high temperature annealing step, performed at a higher temperature than the deposition temperature of the etch stop or barrier layer.

Abstract: There is provided a method of fabricating a lateral MOS transistor, including the steps of (a) forming a gate oxide film on a semiconductor substrate, (b) forming a gate electrode on the gate oxide film, (c) forming a mask covering one of regions of the semiconductor substrate adjacent to the gate electrode, (d) ion-implanting the semiconductor substrate with impurities having a first electrical conductivity as the semiconductor substrate is being rotated around the gate electrode, at an angle relative to the semiconductor substrate to form a channel region in an uncovered region, (e) ion-implanting the semiconductor substrate with impurities having a second electrical conductivity around the gate electrode in self-aligned manner to thereby form source and drain regions. It is preferable that ion-implantation in the step (d) is carried out in the desired number of times.

Abstract: A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O.sub.2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions.

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, in which LDD regions and source/drain regions are provided with a silicide for reducing resistances to prevent short channel, the device including a gate insulating film and a gate electrode formed stacked on a prescribed region of a semiconductor substrate, sidewall spacers formed at both sides of the gate insulating film and the gate electrode, first impurity regions formed in surfaces of the semiconductor substrate under the sidewall spacers, second impurity regions formed in the semiconductor substrate on both sides of the sidewall spacers and the first impurity regions, first silicide films at surfaces of the first impurity regions, and second silicide films at surfaces of the gate electrode and the second impurity regions.

Abstract: A semiconductor substrate having a surface, a field oxide region at the surface and a gate structure above the surface are provided. A sidewall spacer is formed adjacent to the gate structure and a polysilicon layer is formed above the substrate, the polysilicon layer having raised first and second portions above the gate structure and field oxide region, respectively. A masking layer is formed above the polysilicon layer and then blanket etched to expose the raised first and second portions of the polysilicon layer which are subsequently removed to form a raised source/drain region from the polysilicon layer. Since the raised source/drain region is fabricated without using photolithography, high density MOSFETs are readily fabricated.

Abstract: An electrical interconnect includes a substrate having an insulating surface upon which is placed an electrically-conductive cut-link pad and a pair of electrically-conductive lines. The lines are bonded to the cut-link pad and are substantially more resistant to heat flow per unit length than is the cut-link pad. In a preferred embodiment, the thermal resistance per unit length of the cut-link pad is lowered by designing the pad such that its width is greater than the width of either of the lines. A method for cutting a circuit includes directing a laser upon the cut-link pad of an interconnect, as described above. The laser is maintained upon the pad until the cut-link pad is ablated, severing the circuit.

Abstract: The method produces transistor structures with a smaller contact opening, without having to take multiple adjustment allowances into account. Moreover, the method provides two zones of a second conductivity type, which have different dopant concentrations, so that a more gentle transition in the drain doping is obtained. The gentler transition in drain doping effects a lowering in the peak field intensity that can release hot electrons. Thus a degradation of the first insulating layer (gate oxide) caused by hot electrons is prevented.

Abstract: A process for the manufacturing of integrated circuits provides for forming contacts between a conductive material layer and first doped regions of a semiconductor substrate in a self-aligned manner to edges of an insulating material layer which defines active areas of the integrated circuit wherein the doped regions are formed, and second doped regions of the same conductivity type as the first doped regions under the first doped regions, the second doped regions extending partially under the edges of the insulating material layer to prevent short-circuits between the conductive material layer and the semiconductor substrate. The second doped regions are formed by means of implantation of dopants along directions slanted with respect to an orthogonal direction to a surface of the semiconductor substrate at angles and with an energy sufficiently high to make the dopants penetrate in the semiconductor material deeper than the first doped regions and under the edges of the insulating material layer.

Abstract: A method for forming a cavity (30) to a structure such as a poly fuse (114) with a deep etch process whereby a mask is formed over the structure a first dielectric layer (23) and an etch partially through the first dielectric layer is performed. Next, a second dielectric layer (34) is deposited and a second mask is formed for completing the etch to the structure. Finally, an etch through the second dielectric (34) to an area at or near the structure is performed. A resultant device has non-etched second dielectric material on the sidewalls of the etch cavity 30.

Abstract: A method of fabricating a film of active devices is provided. First damaged regions are formed, in a substrate, underneath first areas of the substrate where active devices are to be formed. Active devices are formed onto the first areas. Second damaged regions are formed, in the substrate, between the first damaged regions. The film is caused to detach from a rest of the substrate at a location where the first and second damaged regions are formed.

Abstract: A single-electron device includes a substrate, an insulating film provided on the substrate, a plurality of nanometer-size conductive particles formed in the insulating film along an interface between the substrate and the insulating film, and an electrode provided on the insulating film, wherein the conductive particles have a generally identical size and arranged substantially in a plane at a depth closer to the substrate.

Abstract: A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps: Firstly, a pad oxide layer and a n+ (such as phosphorus) doped oxide layer is successively formed on the silicon substrate. Then, a nitride layer is deposited on all surfaces as an antireflection coating layer. After coating a patterned mask on the nitride layer to define a plurality of buried bit line regions, a dry etch is used to etch the unmask region till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and an oxidation process to grow an oxynitride layer on resultant surface and form buried bit line using dopants in the oxide layer as a diffusion source. After refilling a plurality of trenches with n+ doped silicon layer, a planarization process such as CMP is done to form a plain surface using the nitride layer as an etching stopped layer.

Abstract: Each region of multiple regions on a semiconductor substrate is imaged in an exposure field defined by a reticle. The regions are separated and electrically isolated within the semiconductor substrate by an isolation such as a field oxide or trench isolation. The regions are interconnected by imaging using a stitching reticle having an exposure field overlapping a plurality of the regions. The combination of reticle-imaged fields effectively increases the size of a field formed using a step and repeat technique while achieving high imaging resolution within the combined regions. Similarly, a plurality of integrated chip sets, including microprocessor, memory, and support chips, are constructed on a single semiconductor wafer using separate reticle imaging of each of the plurality of integrated chip sets. The different circuits are interconnected using a stitch mask and etch operation that combines the regions.