Abstract: Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure.

Abstract: In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material.

Abstract: Over the principal surface of a semiconductor substrate body containing an impurity of a predetermined conduction type, there is formed an epitaxial layer which contains an impurity of the same conduction type as that of the former impurity and the same concentration as the designed one of the former impurity. After this, there are formed a well region which has the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said epitaxial layer. The well region is formed with the gate insulating films of MIS.FETs.

Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).

Abstract: A semiconductor device (60) may comprise a semiconductor layer (12) having an outer surface (20). A plurality of gates (18) may be disposed over the outer surface (20) of the semiconductor layer (12). An isolation cover (30) may be disposed over the gates (18). An implant screen (40) may be grown on the outer surface (20) of the semiconductor layer (12) between the isolation covers (30) of the gates (18).

Abstract: An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element.

Abstract: An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Abstract: A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described.

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Abstract: A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the specified conductivity type is introduced, typically simultaneously, (a) into part of a first channel zone of the material of the specified conductivity type to define a threshold channel portion (66) more heavily doped than a main channel portion (65) and (b) into substantially all of a second channel zone of the material of the specified conductivity type. First and second gate electrodes (69 and 141) are provided respectively above, and insulatingly spaced apart from, the first and second channel zones.

Abstract: This invention is a processing method for forming MOS transistors. The method uses chemical mechanical polishing to self align an MOS transistor gate electrode to the channel region in both the width and length directions. The method enables metal interconnect lines to make borderless connections to MOS gate electrodes directly over channel regions, and allows borderless connections to be made to source and drain regions, thereby improving layout density of small transistors. The method enables interconnect lines to be patterned on a planar surface, which facilitates the etching of very narrow and closely spaced lines. The method does not require any Shallow Trench Isolation (STI), and does not require Local Oxidation of Silicon (LOCOS), thereby resulting in little damage to the silicon. The method also prevents plasma damage of very thin gate dielectrics during processing.

Abstract: A process for forming high voltage and low voltage transistors on the same substrates includes first forming a poly gate (16) over layer gate oxide (10) on a substrate (12). An LDD implant is then performed, followed by the formation of a nitride cap (30) over the gate (16). The cap (30) is not disposed over gate electrodes associated with low voltage transistors. Thereafter, the source/drain implant is performed which forms source/drain regions (40) and (42). The cap (30) prevents the introduction of dopants into the gate electrode (16) during the source/drain implant step. This effectively increases the gate oxide width due to a larger depletion region at the oxide/polysilicon gate boundary as compared to the low voltage transistors with the higher dopant levels and the gate electrode.

Abstract: Disclosed is a vertically oriented capacitor structure, which is of particular usefulness in MOS DRAM memory modules. The structure has upper and lower polysilicon capacitor plates separated by a dielectric layer, each of the plates and dielectric layers sloping at an angle with of about 80-85 degrees with respect to an underlying silicon substrate. As such, the novel capacitor is formed in a sloped contact opening. The contact area of electrical connection of the lower capacitor plate with an underlying active region has a sufficiently small horizontal cross-section that the contact area will not extend laterally beyond the active region and leakage will not occur. A method for forming the contact opening is disclosed and comprises first, the formation of an active region, preferably located between two insulating bird's beak regions, and covering the active area with a thin layer of oxide etch barrier material. A polysilicon layer is then formed above the oxide etch barrier.

Abstract: The present invention proposes a method for fabricating a high-density shallow trench contactless nonvolatile memory. First, a stacked pad oxide/silicon nitride layer is deposited on the substrate and the buried bit line region is defined by a photoresist. An anisotropic etching follows to etch the silicon layer and then the n+ impurity ions are implanted to form the source and drain. After stripping the photoresist, a high temperature steam oxidation process is used to grow a thick field oxide, and the doped ions are active and driven in to form the buried bit lines simultaneously. The silicon nitride layer and the pad oxide layer are then removed, and the silicon substrate is recessed by using the field oxide as an etching mask. After rounding the trench corners by using thermal oxidation and etching back processes, a thin silicon oxy-nitride film is regrown. An in-situ doped polysilicon film is deposited to refill the trench region and then etch back by using a CMP process to form the floating gates.

Abstract: A cellular insulated gate bipolar transistor ("IGBT") device has a reduced length of the channels of the individual cells that is formed by reducing the channel drive in time from the customary 120 minutes at 1175.degree. C. to between 60 and 90 minutes at 1175.degree. C. The process also permits the use of a higher minority carrier lifetime killing electron radiation dose to improve switching power loss while reducing SOA by only a small value. Alternatively, the increased concentration region located in the active region between spaced bases is initially driven in at a temperature of about 1175.degree. C. for about 12 hours, rather than the customary 8 hours, and the channel drive in time is reduced from 120 minutes to 60 minutes. The shorter channel length, when combined with the deeper enhancement region, allows for higher lifetime electron irradiation doses or heavy metal diffusion temperatures.

Abstract: A manufacturing method of a semiconductor device of the present invention comprises the steps of forming an amorphous layer on an upper layer of the impurity diffusion layer made of silicon by virtue of ion-implantation, forming a cobalt film on the impurity diffusion layer, forming a cobalt silicide layer made of Co.sub.2 Si or CoSi on an upper layer of the amorphous layer at a low temperature by reacting the cobalt film to silicon in the impurity diffusion layer in virtue of first annealing, then removing the cobalt film which has not reacted, and changing Co.sub.2 Si or CoSi constituting the cobalt silicide layer into CoSi.sub.2 to have low resistance and also rendering the cobalt silicide layer to enter into a depth identical to or deeper than an initial depth of the amorphous layer in virtue of second annealing.

Abstract: A method of manufacturing a raised source/drain semiconductor device is disclosed. When the shallow junction technique is applied, over etching of the source/drain regions during contact etching and salicide processing will lead to current leakage. The invention provides a method which comprises depositing a buffer conductive layer above the substrate and removing a portion of this layer to form buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions.

Abstract: Disclosed is a MOS transistor and a fabrication process for the MOS transistor. Each gate electrode pattern made of silicon is formed on a gate oxide film formed on a silicon base body. An impurity is doped in the silicon base body using the gate electrode patterns as a mask, followed by activation of the impurity thus doped, to form diffusion layers in a surface layer of the silicon base body. An interlayer insulating film is formed in such a manner as to cover the gate electrode patterns. An upper portion of the interlayer insulating film is removed to expose the upper portion of each gate electrode pattern. The gate electrode pattern thus exposed is removed by selective etching. After that, a recessed portion formed by removal of each gate electrode pattern is embedded with a metal material, to form a CMOS transistor.

Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.