Abstract: A reduced metal-rich interface between a poly and metal silicide layer is achieved by insitu doping the metal silicide layer.

Abstract: A process of forming on an integrated circuit substrate at least two different gate masks having different lengths is described. The process includes: (i) providing the integrated circuit substrate having a surface; (ii) depositing on the surface a gate layer; and (iii) masking portions of the gate layer using a reticle having at least two die patterns including a first die pattern defining an image of a first gate electrode having a first length and a second die pattern defining an image of a second gate electrode having a second length, the first length being different from the second length and relative positioning of the image of the first gate electrode in the first die pattern and of the image of second gate electrode in the second die pattern is substantially similar.

Abstract: Semiconductor devices and fabrication processes which rely on the use of sacrificial gate electrode plugs are provided. In one embodiment, a germanium bearing plug is used to form a gate electrode. The germanium plug may advantageously be removed using a solution which leaves underlying portions of the oxide layer intact. In another embodiment, spacers are formed adjacent sidewalls of a sacrificial plug and active regions are formed adjacent the sacrificial plug. The sacrificial plug is then removed to form an opening between the spacers and a conductive layer is deposited over the substrate to form a gate electrode and active region contacts.

Abstract: A gate is formed on a semiconductor substrate by using a SiON film as both a bottom anti-reflective coating (BARC) and subsequently as a hardmask to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, and a SiON film over the conductive layer. The resist mask is formed on the SiON film. The SiON film improves the resist mask formation process and then serves as a hardmask during subsequent etching processes. Then the wafer stack is shaped to form one or more polysilicon gates by sequentially etching through selected portions of the SiON film and the gate conductive layer as defined by the etch windows in the original resist mask. Once the gate has been properly shaped, any remaining portions of either the resist mask or the SiON film are then removed.

Abstract: A method for forming a semiconductor device includes providing a semiconductor body having source and drain regions therein and a gate electrode on a portion of a surface of such body between the source and drain regions. A dielectric layer is provided on the surface of the semiconductor body over the source and drain regions. A dielectric material is formed over the dielectric layer and over the gate electrode. An inorganic, dielectric layer is formed over the semiconductor body dielectric material. The inorganic, dielectric layer is patterned into a mask to expose selected portions of the dielectric material, such portions being over the source and drain regions. An etch is brought into contact with the mask. The etch removes the exposed underlying portions of the dielectric material and exposed underling portions of the dielectric layer to thereby expose the portions of the source and drain regions.

Abstract: A method for producing a MIS structure on silicon carbide is provided. Given application of a known CVD method for occupying the surface of a SiC substrate provided with a gate oxide with the silicon serving as gate material, stationary positive charges arise in the region of the oxide/SiC boundary surface whose extremely high effective density (Q.sub.tot >10.sup.12 cm.sup.-2) disadvantageously influences the electrical properties of the finished component. The present method modifies the deposition conditions for the silicon serving as a gate material. Thus, the silicon is deposited from the vapor phase at a temperature of T<580.degree. C. and is thus amorphously applied. During the subsequent doping (drive-in of phosphorous at T>800.degree. C.), the amorphous silicon converts into the polycrystalline condition.

Abstract: Multiple implants are performed in an integrated circuit substrate by implanting ions into a face thereof. Then, a gate insulating layer and a gate electrode are formed on the face of the integrated circuit substrate after performing the multiple implants in the integrated circuit substrate. Preferably, ions are not implanted into the integrated circuit substrate through the face after forming the gate insulating layer and the gate electrode on the face of the integrated circuit substrate. By preferably performing all implants prior to forming a gate insulating layer, the gate insulating layer is not degraded by implanting ions into the face of the integrated circuit substrate through the gate insulating layer.

Abstract: A method of manufacturing MOS device including the steps of providing a semiconductor substrate that has a device isolation structure thereon, and then depositing a gate oxide layer, a polysilicon layer and an anti-reflection coating in sequence over the substrate. Next, a gate structure is patterned out of the gate oxide layer, the polysilicon layer and the anti-reflection coating. Then, spacers are formed on the sidewalls of the gate structure. Thereafter, a metal silicide layer is formed over source/drain regions. After that, an inter-layer dielectric (ILD) layer is formed over the gate structure and the entire substrate. Then, the inter-layer dielectric layer is planarized to expose the anti-reflection coating. Next, the anti-reflection coating is removed, and then a barrier layer is deposited over the inter-layer dielectric layer and the polysilicon layer. Subsequently, a conductive layer is deposited over the barrier layer.

Abstract: A method of fabricating a semiconductor device which includes the steps of forming a trench (4), and repeating the formation and removal of an oxide film (a sacrificial oxide film) twice to provide a rounded configuration (5b) of an opening portion of the trench (4) and a rounded configuration (6b) of a bottom thereof and to draw defects in a semiconductor layer into a silicon oxide film (8), reducing the defects adjacent the inner wall of the trench (4), whereby electric field concentration on a gate is prevented and the mobility of carriers in channels is improved for an improvement in characteristic, particularly an on-state voltage, of a power device.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV. A damascene process can be utilized to fabricate the MOSFETs.

Abstract: A method of manufacturing a semiconductor device with raised source/drain. This method eliminates the problem which is often experienced when the shallow junction technique is applied, in which over-etching of the source/drain region during the contact etching and the salicide process can lead to current leakages. The improved method includes the steps of forming a buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions. A related semiconductor structure made by the method has a plurality of bi-flange shape side wall spacers by which the semiconductor structure not only elevates the doped regions, it also provides an improved capability to suppress the electric bridges between the gate electrode and source/drain regions, respectively.

Abstract: A method for fabricating a field device transistor includes forming a gate oxide layer of the field device transistor by performing a thermal oxidation process. By properly controlling the thickness of the gate oxide layer, the threshold voltage of the field device transistor can be suppressed in under 5 volts to provide sufficient protection for the internal circuit. The method of the invention includes forming a gate oxide layer of a field device transistor by performing a thermal oxidation process instead of a field oxide layer in order to obtain a better control on the thickness of the gate oxide layer.

Abstract: Methods for making surface channel MOS transistors.

Abstract: The present invention is directed to a new and improved technique for formation of metal oxide semiconductor field effect transistors. In particular, the method involves formation of an initial gate structure that is wider than the desired final channel length of the completed transistor. Thereafter, an initial heavy-doping step is applied to the drain and source regions of the device. The width of the gate structure is then patterned and etched back to the desired final channel length of the device. A second, light-doping LDD implant is performed to complete the source and drain regions of the finished device.

Abstract: A process for fabricating thin film transistors in which the active layer is an organic semiconducting material with a carrier mobility greater than 10.sup.-3 cm.sup.2 /Vs and a conductivity less than about 10.sup.-6 S/cm at 20.degree. C. is disclosed. The organic semiconducting material is a regioregular (3-alkylthiophene) polymer. The organic semiconducting films are formed by applying a solution of the regioregular polymer and a solvent over the substrate. The poly (3-alkylthiophene) films have a preferred orientation in which the thiophene chains has a planar stacking so the polymer backbone is generally parallel to the substrate surface.

Abstract: High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Field oxide regions, gates, spacers, and source/drain implants are initially formed. A layer of silicon is then deposited. A protective non-contuctive film is then formed and anisotropically etched to expose the silicon layer on the source/drain regions and the top surfaces of the gates, and to form protective spacers on the edges of the field oxide regions and on the side surfaces of the gates. A layer of cobalt is thereafter deposited and silicidation is performed, as by rapid thermal annealing, to form a low-resistance cobalt silicide while consuming the silicon film. The consumption of the silicon film during silicidation results in less consumption of substrate silicon, thereby enabling the formation of ultra-shallow source/drain junctions without junction leakage, allowing the formation of cobalt silicide contacts at optimum thickness and facilitating reliable device scaling.

Abstract: A method of rapid thermal processing (RTP) of a silicon substrate is presented, where a very low partial pressure of reactive gas is used to control etching and growth of oxides on the silicon surface.

Abstract: High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

Abstract: Improved etching of sub-micron diameter via or contact holes in integrated circuits is achieved by first coating the dielectric layer through which the hole is to be etched with successive layers of titanium and silicon oxynitride. This is followed by coating with a conventional photoresist mask which is thinner than usual, thereby allowing for improved resolution. Etching is carried out in two stages. First, only the oxynitride and titanium layers are etched with minimal penetration into the dielectric. In this way a hard mask of titanium is formed. It's optical fidelity is excellent since the combination of silicon oxynitride and titanium act as a very efficient anti-reflection coating. Etching of the hole is then completed using a different etch which also removes the remaining photoresist, the silicon oxynitride as well as some of the titanium.

Abstract: A method of forming a field effect transistor relative to a semiconductor substrate, where the transistor has a gate which defines a resultant lateral expanse of semiconductive material therebeneath for provision of a transistor channel region, includes a) providing a conductive gate layer over a semiconductor substrate; b) patterning the conductive gate layer into a first gate block, the first gate block having a first lateral expanse which is greater than the resultant lateral expanse; c) providing an insulating dielectric layer over the first gate block; d) providing a patterned layer of photoresist over the first gate block and the insulating dielectric layer, the patterned photoresist comprising a photoresist block positioned over and within the first lateral expanse of the first gate block; e) with the patterned photoresist in place, etching the insulating dielectric layer selectively relative to the first gate block; f) after etching the insulating dielectric layer and with the patterned photoresist in