Abstract: A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.

Abstract: An analog switch circuit of an embodiment includes a CMOS analog switch, a first gate drive circuit, and a second gate drive circuit, a gate operating withstand voltage of the CMOS analog switch being VGT, an enable signal and a control signal being inputted to the first gate drive circuit and the second gate drive circuit. Assuming that VGT<VSH?(2×VGT), in a case where the enable signal is 0, the second gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of a PMOS when the control signal is 0, and the first gate drive circuit outputs a signal of voltage (VSH/2) to a gate terminal of an NMOS when the control signal is 1.

Abstract: Laboratory equipment with flammable refrigerant and connected to at least two different electrical potentials for supplying the equipment with electrical energy. An electrical switch arrangement has first and second switches for electrical separation from, respectively, the first and second potentials. A sequence controller switches on the first switch and thereafter the second switch. A monitoring device is connected via a first contact on the equipment side to the first switch and via a second contact on the mains side to an electrical potential other than the first electrical potential for detecting a switched-on state of the first switch and signaling the detection to the sequence controller. When the monitoring device signals a switched-on state, the sequence controller blocks operation of the equipment as a function of the signaled switched-on state and whether the first switch is expected to be switched on or switched off.

Abstract: A method and apparatus for generating an RF signal uses digital signal components to generate a synthesized RF signal having a plurality of frequency components. An analog filter is used to filter the synthesized RF signal. The analog filter is a tunable, active feedback circuit having one or more variable resonators and a variable gain block connected in a signal loop that is defined by a passband. The analog filter is tuned such that the passband of the analog filter overlaps one or more desired frequency components of the plurality of frequency components of the synthesized RF signal, and such that the passband has a relative bandwidth of about 1% or less.

Abstract: A level shifter and a chip with the level shifter are shown. Between the input pair and the cross-coupled output pair, there are a first protection circuit and a second protection circuit. An overdrive voltage, which is double the nominal voltage of the level shifter plus a delta voltage, is applied to the level shifter. The first protection circuit has a first voltage-drop circuit that compensates for the delta voltage. The second protection circuit has a second voltage-drop circuit that compensates for the delta voltage.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: An apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

Abstract: A vehicle audio video navigation (AVN) system may be provided that includes: a plurality of source providers which receives a sound source; a user operation unit which selects at least one of a plurality of the sound sources input from the plurality of the source providers and selects a focusing zone of the sound source; a processor which generates a sound source signal for focusing an output of the selected sound source on the focusing zone; and a multi-channel amplifier which outputs the sound source signal. As a result, the focusing zone of each sound output within a vehicle can be individually controlled. Particularly, the focusing zone of each sound can be easily selected and controlled without changing the location of the speaker within the vehicle. Also, the sound source and the focusing zone within the vehicle can be selected and controlled only by adding an external processor without replacing the AVN device provided in the vehicle.

Abstract: Techniques facilitating a quantum gate between qubits using a tunable coupler are provided. In one example, a quantum coupler device can comprise a Josephson ring modulator (JRM) that is operatively coupled to first and second qubits in a balanced bridge topology via respective first and second capacitive devices. The JRM provides tunable coupling between the first and second qubits.

Abstract: When a radio-frequency module is viewed in plan in a thickness direction of a mounting substrate, an electronic component overlaps an IC component. The electronic component includes four or more filters, each of which includes an input terminal and an output terminal. The IC component includes a first switch connected to the input terminals of at least four of the four or more filters and a second switch connected to the output terminals of the at least four filters. The input terminals of the at least four filters are in a first region including a center of the electronic component when viewed in plan in the thickness direction of the mounting substrate. The output terminals of the at least four filters are in a second region between the first region and a perimeter of the electronic component when viewed in plan in the thickness direction of the mounting substrate.

Abstract: The present disclosure provides a driving circuit, a driving IC, and a driving system, relating to the technical field of electronic circuits. The driving circuit comprises a control module and a driving signal output module, the control module is electrically connected to the driving signal output module, and the driving signal output module is configured to be electrically connected to a to-be-driven device, wherein the driving signal output module comprises at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; and the control module is configured to control a closed state of the at least two transistors, so as to control an operation state of the to-be-driven device.

Abstract: Systems and methods for packaging an acoustic device in an integrated circuit (IC) include walls formed on a wiring substrate. The walls have a height which is just shorter than an expected height of a solder bump on the acoustic device after solder reflow. The walls are positioned on either side of the acoustic device and a small portion lies underneath an exterior edge of the acoustic device such that a relatively small gap is formed between an upper surface of the wall and the lower surface of the acoustic device. By providing a small gap between wall and acoustic device, encroachment by an encapsulating material into a keep out zone of the acoustic device is minimized.

Abstract: A high-frequency amplifier for an active EMI filter with a symmetric class B emitter-follower output stage driven by a driver stage, with a sense output resistor. Both terminals of the sense resistor are brought to the noninverting, respecting inverting input of the driver stage through two dividers of the same ratio, in a global voltage feedback loop. The amplifier is configured to provide a high output impedance at 10 kHz and up to 100 MHz, a peak-to-peak output current of 2-10 ampere and a low quiescent current of less than 400 mA. The invention includes EMI filters with such a high-frequency current source, for example in the current-sense current-inject feedback configuration.

Abstract: Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.

Abstract: A load switch circuit includes a power transistor, the first terminal is configured to receive the power supply voltage, and the second terminal is the output terminal of the load switch circuit and is coupled with an external inductive load; a clamping module including at least a mutually coupled clamping unit and a driving unit; the clamping unit, including a voltage-current converter and a first resistor, the first resistor is coupled between the output terminal of the voltage-current converter and the second terminal of the power transistor, the output terminal of the drive unit is coupled to the control terminal of the power transistor when the difference between the power supply voltage and the output voltage of the power transistor is greater than or equal to the preset clamping threshold, and the clamping unit outputs an effective drive control signal to the driving unit.

Abstract: A compensation signal generator generates a compensation signal for canceling an electromagnetic noise on a connection line on the basis of a detection signal of a noise detector. A compensation signal injector injects the compensation signal into the connection line. A compensation signal detector outputs a detection signal of the compensation signal. A low-frequency component subtraction unit amplifies a component in a predetermined first frequency region of the detection signal and negatively feeds back the amplified component to the compensation signal generator. An intermediate frequency component addition unit positively feeds back a component of a predetermined second frequency that is higher than the first frequency region in the detection signal to the compensation signal generator.

Abstract: A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Abstract: Reducing a sensitivity of an electromechanical sensor is presented herein. The electromechanical sensor comprises a sensitivity with respect to a variation of a mechanical-to-electrical gain of a sense element of the electromechanical sensor; and a voltage-to-voltage converter component that minimizes the sensitivity by coupling, via a defined feedback capacitance, a positive feedback voltage to a sense electrode of the sense element—the sense element electrically coupled to an input of the voltage-to-voltage converter component. In one example, the voltage-to-voltage converter component minimizes the sensitivity by maintaining, via the defined feedback capacitance, a constant charge at the sense electrode. In another example, the electromechanical sensor comprises a capacitive sense element comprising a first node comprising the sense electrode. Further, a bias voltage component can apply a bias voltage to a second node of the electromechanical sensor.

Abstract: A system includes multiple sensors and, for each sensor, a respective sensor controller of multiple sensor controllers. Each sensor controller is configured to implement a respective decimation filter that is configured to generate a single output value from multiple input samples generated by a corresponding sensor of the multiple sensors. The system further includes a master sensor controller of the multiple sensor controllers, which is configured to generate a sync signal upon receiving a threshold number of input samples. Each sensor controller other than the master sensor controller is configured to monitor sync signals generated by the master sensor controller and to provide an output value generated from input samples upon determining that the master sensor controller generated a sync signal.

Abstract: Provided is a clock signal generation circuit. The clock signal generation circuit includes a control word generation circuit, an initial clock generation circuit and a spread spectrum clock generation circuit, wherein the control word generation circuit is connected to the initial clock generation circuit and the spread spectrum clock generation circuit; the initial clock generation circuit is further connected to the spread spectrum clock generation circuit.