Patents Examined by Jung Kim
-
Patent number: 11831304Abstract: A transceiver circuit includes a first interface and a second interface that are connected to an optical transceiver device, a receiver circuit, a transmitter circuit, and a compensation circuit. The receiver circuit includes a differential amplifier, where a first phase input terminal of the differential amplifier is coupled to the first interface, and where a second phase input terminal of the differential amplifier is coupled to the second interface. The transmitter circuit includes a first transistor, where a terminal of the first transistor is coupled to the second phase input terminal, and where another terminal of the first transistor is coupled to a ground terminal. The compensation circuit is configured to provide a leakage path for the first phase input terminal, or provide a compensation current for the second phase input terminal.Type: GrantFiled: December 28, 2021Date of Patent: November 28, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Furong Xiong, Kai Li, Wei Song
-
Patent number: 11815406Abstract: Methods and apparatus for extracting temperature information for an array from a signal through first and second contacts based on temperature dependent properties of the a PN junction. An example method includes connecting first and second PN junctions to a bias source to reverse bias the first and second PN junctions, connecting a first contact to the first PN junction, connecting a second contact to N type material forming a junction with P type material of the first PN junction, and extracting temperature information for the first PN junction from a signal through the first and second contacts based on temperature dependent properties of the first PN junction.Type: GrantFiled: April 14, 2021Date of Patent: November 14, 2023Assignee: Allegro MicroSystems, LLCInventors: Joseph James Judkins, III, Bryan Cadugan
-
Patent number: 11817828Abstract: An amplifier circuitry includes a first amplifier, a second amplifier, a voltage generating circuitry, and a control circuitry. The first amplifier circuitry configured to amplify a first signal. The second amplifier circuitry configured to amplify a second signal which forms differential signals together with the first signal. The voltage generating circuitry configured to generate at least one of a first bias voltage to be applied to the first signal and a second bias voltage to be applied to the second signal. The control circuitry configured to control the voltage generation circuitry so as to decrease a difference between a DC component of an output of the first amplifier circuitry and a DC component of an output of the second amplifier circuitry.Type: GrantFiled: September 4, 2020Date of Patent: November 14, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Tong Wang
-
Patent number: 11811405Abstract: A resonant gate driver 200A includes an H-bridge circuit and a resonant inductor integrated on a semiconductor substrate. A first leg of the H-bridge circuit includes a first high-side transistor, a first output node, and a first low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a first region defined along a first side. The second leg of the H-bridge circuit includes a second high-side transistor, a second output node, and a second low-side transistor such that they are arranged side-by-side in a first direction (x direction) in a second region defined along a second side. A resonant inductor is a parasitic inductance that occurs in a coupling means that electrically couples the first output node and the second output node.Type: GrantFiled: March 10, 2022Date of Patent: November 7, 2023Assignee: ROHM CO., LTD.Inventor: Hiroki Niikura
-
Patent number: 11811411Abstract: A glitch filter system includes an input stage to receive an input signal, a first output to provide a first digital signal, and a second output to provide a second digital signal. A C-element of such system receives the first digital signal and the second digital signal and provides a third digital signal at a first logic state in response to each of the first and second digital signals having a second logic state opposite the first logic state. An output latch of such system provides an output signal at the second logic state in response to the first logic state of the third digital. The output latch also receives the first and second digital signals to maintain the first logic state of the third digital signal in response to one of the first and second digital signals changing from the second logic state to the first logic state.Type: GrantFiled: May 2, 2022Date of Patent: November 7, 2023Assignee: Texas Instruments IncorporatedInventors: Abhijit Kumar Das, Ryan Alexander Smith
-
Patent number: 11804837Abstract: A switch circuit electrically connected to a power source and a first control source and including a plurality of switch bridge arms is provided. Each of the plurality of switch bridge arms includes a first switch and a second switch electrically connected in series. A loop formed by the first switch, the second switch and the power source is defined as a power loop. A loop formed by the first control source and the first switch is defined as a first control loop. A first mutual inductance is formed between the power loop and the first control loop. Among all the first switches, the first switch with the longer power loop has the smaller first mutual inductance.Type: GrantFiled: June 15, 2022Date of Patent: October 31, 2023Assignee: DELTA ELECTRONICS, INC.Inventors: Boyi Zhang, Ruxi Wang, Peter Mantovanelli Barbosa
-
Patent number: 11804255Abstract: A memory device includes a voltage generator configured to generate a reference voltage for transmission to at least one component of the memory device. The voltage generator includes a first input to receive a first signal having a first voltage value. The voltage generator also includes a second input to receive a second signal having a second voltage value. The voltage generator further includes a first circuit configured to generate third voltage and a second circuit coupled to the first circuit to receive the third voltage value, wherein the second circuit receives the first signal and the second signal and is configured to utilize the third voltage value to facilitate comparison of the first voltage value and the second voltage value to generate an output voltage.Type: GrantFiled: August 4, 2021Date of Patent: October 31, 2023Assignee: Micron Technology, Inc.Inventors: Zhi Qi Huang, Wei Lu Chu
-
Patent number: 11799472Abstract: A drive circuit for a switching element includes: a first power supply; a second power supply; a power supply switching unit that switches the first and second power supplies for applying the drive voltage based on a drive command; and an output switching unit outputting an output voltage switching signal to the second power supply that the output voltage of the second power supply becomes zero in a part of a drive period of the switching element including at least a part of an on-drive period, and the output voltage becomes a predetermined voltage other than zero in a remaining part of the drive period including at least a part of an off-drive period.Type: GrantFiled: October 8, 2021Date of Patent: October 24, 2023Assignee: DENSO CORPORATIONInventor: Kazunori Watanabe
-
Patent number: 11799327Abstract: A system configured to deliver wireless charging power to electronic devices can include a programmable radio-frequency generator capable of generating a beam of electromagnetic pulsed radiation and plurality of solid-state amplifiers to amplify the beam of electromagnetic pulsed radiation. The amplified beam of electromagnetic pulsed radiation can be configured to wirelessly charge electronic devices at distances greater than about 100 meters.Type: GrantFiled: February 23, 2022Date of Patent: October 24, 2023Assignee: Epirus, Inc.Inventors: Harry Bourne Marr, Jr., William Griffin Dower, Yiu Man So, Jar Jueh Lee, Jeffery Jay Logan
-
Patent number: 11799430Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal.Type: GrantFiled: August 11, 2020Date of Patent: October 24, 2023Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kei Takahashi, Takeshi Aoki, Munehiro Kozuma, Takayuki Ikeda
-
Patent number: 11784646Abstract: An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.Type: GrantFiled: June 2, 2022Date of Patent: October 10, 2023Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY, LIMITEDInventors: Ying Huang, Changlin Huang, Jing Ding, Qingchao Meng
-
Patent number: 11784617Abstract: Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.Type: GrantFiled: October 30, 2020Date of Patent: October 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
-
Patent number: 11784612Abstract: A signal detection circuit includes: a first capacitor having a first terminal connected with a first main terminal of a switching element; a second capacitor having a first terminal connected with a second main terminal of the switching element; and a detection circuit having a differential circuit configuration. The detection circuit receives, as input signals, a signal from a second terminal of the first capacitor and a signal from a second terminal of the second capacitor, detects detection target signals based on the input signals. The detection target signals include a signal of the first main terminal of the switching element and a signal of the second main terminal of the switching element.Type: GrantFiled: December 8, 2021Date of Patent: October 10, 2023Assignee: DENSO CORPORATIONInventors: Takasuke Itou, Tomohiro Nezuka, Yasuaki Aoki, Yuuta Nakamura, Takashi Yoshiya
-
Patent number: 11777490Abstract: A solid-state relay includes a semiconductor switch and a voltage boost block. The semiconductor switch has a control input, which causes the semiconductor switch to shift from an open, non-conducting position to a closed, conducting position when a voltage is applied to the control input. The voltage boost block includes a boost converter and a ground connector. A voltage output of the semiconductor switch is electrically connected to a voltage input of the boost converter. A voltage output of the boost converter is electrically connected to the control input. The ground connector of the boost converter is electrically connected to a voltage input of the semiconductor switch When the semiconductor switch is in the closed position, the semiconductor switch is maintained in a closed position in the absence of another control signal.Type: GrantFiled: August 12, 2022Date of Patent: October 3, 2023Assignee: AXIS ABInventor: Ond{hacek over (r)}ej Vrzala
-
Patent number: 11777488Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.Type: GrantFiled: March 24, 2022Date of Patent: October 3, 2023Assignee: Micron Technology, Inc.Inventors: Hiroshi Akamatsu, Yuan He, Toru Ishikawa
-
Patent number: 11777187Abstract: A method of operating a reconfigurable quadrature coupler is disclosed. The method includes determining a first switchable impedance to provide a second port reflection coefficient by operating a coupled port transformer, which coupled port transformer is coupled to a second port having a coupled port transmission line connected to a first transistor; determining a second switchable impedance to provide a third port reflection coefficient by operating an isolation port transformer, which isolation port transformer is coupled to a third port having an isolation port transmission line connected to a second transistor; and determining a fourth switchable impedance to provide a fourth port reflection coefficient by operating a through port transformer, which through port transformer is coupled to a fourth port having a through port transmission line connected to a third transistor, and switching on or off selected ones of the first, second, and third transistors by operating a controller.Type: GrantFiled: November 15, 2022Date of Patent: October 3, 2023Assignee: Qorvo US, Inc.Inventor: Charles Forrest Campbell
-
Patent number: 11777479Abstract: Embodiments relate to identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.Type: GrantFiled: October 31, 2022Date of Patent: October 3, 2023Assignee: APPLE INC.Inventors: Helena Deirdre O'Shea, Ali Moaz, Tim Schoenauer, Rahmi Hezar
-
Patent number: 11777496Abstract: A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output circuit comprises an input transistor which comprises a gate terminal coupled to the output terminal of the voltage-mode filter circuit, and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current-mode output circuit.Type: GrantFiled: August 22, 2022Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Sudipto Chakraborty, John Francis Bulzacchelli, Daniel Joseph Friedman
-
Patent number: 11777487Abstract: A gate driver circuit includes an isolated gate driver power supply circuit. The isolated gate driver power supply circuit includes a coreless transformer including a primary winding and a secondary winding. The secondary winding is wound about a toroid-shaped, non-magnetic body and the primary winding is a single turn primary winding to reduce capacitance coupling between the primary winding and the secondary winding. The isolated gate driver power supply circuit also includes a resonance converter coupled to the coreless transformer, wherein the resonance converter is configured to enable the isolated gate driver power supply circuit to generate an output voltage independent of load.Type: GrantFiled: April 7, 2022Date of Patent: October 3, 2023Assignee: GE Precision Healthcare LLCInventors: Juan Antonio Sabate, Eladio Clemente Delgado
-
Patent number: 11770119Abstract: A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.Type: GrantFiled: June 29, 2022Date of Patent: September 26, 2023Assignee: Infineon Technologies AGInventors: Zheming Li, Mark-Matthias Bakran, Daniel Domes, Robert Maier, Franz-Josef Niedernostheide