Abstract: Provided is a work machine or the like which can switch between a power supply state and a power supply cutoff state of an actual machine control device irrespective of switching on or off an actual machine switch. On switching an actual machine switch 81 from off to on, a first power supply route from an actual machine power source 80 to an actual machine control device 400 is formed. Consequently, a second power supply route from the actual machine power source 80 to the actual machine control device 400 is formed. Then, the first power supply route is cut off, while the second power supply route not through the actual machine switch 81 is maintained.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: Switch drive circuits include galvanically isolated switch circuits with power transfer from the switch driver input side to the switch side. A switch drive circuit uses a single transformer to transfer control signals to a secondary side for control of the switch along with power to a secondary side circuit to drive the switch in response to the control signals. By detecting the control signal first before drawing current, the effects of leakage inductance in the transformer are reduced.

Abstract: Voltage-to-current converters that include two current mirrors are disclosed. In an example voltage-to-current converter each current mirror is a complementary current mirror in that one of its input and output transistors is a P-type transistor and the other one is an N-type transistor. Such voltage-to-current converters may be implemented using bipolar technology, CMOS technology, or a combination of bipolar and CMOS technologies, and may be made sufficiently compact and accurate while operating at sufficiently low voltages and consuming limited power.

Abstract: Apparatus and methods for compensating supply sensitive circuits for supply voltage variation are provided. An electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a group of integrated circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a supply sensing circuit that generates a sense signal based on a local voltage level of the supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between the nominal voltage level and the local voltage level of the supply voltage, and a signal processing circuit biased by the bias signal.

Abstract: Systems and techniques that facilitate mapping a heavy-hex qubit connection topology to a rectilinear physical qubit layout are provided. In various embodiments, a device can comprise a qubit lattice on a substrate. In various aspects, the qubit lattice can comprise one or more first qubit tiles. In various cases, the one or more first qubit tiles can have a first shape. In various instances, the qubit lattice can further comprise one or more second qubit tiles. In various cases, the one or more second qubit tiles can have a second shape. In various aspects, the one or more first qubit tiles can be tessellated with the one or more second qubit tiles.

Abstract: A disclosed under-voltage lockout (UVLO) circuit includes an automatic UVLO threshold configuration. The UVLO circuit may include an over-voltage protection circuit that receives power from a power source, a peak detector that detects a peak voltage output for the power source, a voltage threshold generator that sets a UVLO threshold based on the peak voltage output, and a comparator that compares an instantaneous voltage with the UVLO threshold and configures an operating mode of a device based on the comparison.

Abstract: An integrated circuit (IC) includes first, second, third, and fourth transistors, first and second current source devices, and a trim circuit. The first transistor has a first control input and a first current terminal. The second transistor has a second control input and a second current terminal. The third transistor had a third control input and third and fourth current terminals. The fourth transistor has a fourth control input and fifth and sixth current terminals. The first current source is coupled between a first power supply node and the third current terminal. The second current source is coupled between the first supply node and the fifth current terminal. The trim circuit is coupled between the fourth current terminal and a second power supply node, and is coupled between the sixth current terminal and the second power supply node. The trim circuit includes a resistive digital-to-analog converter (RDAC) circuit.

Abstract: A circuit includes a first delay filter, a first comparator, an inverter, a second delay filter, a second comparator, an OR gate, and a latch. A first delay filter input is coupled to an inverter input. The first comparator has a first comparator input coupled to a first delay filter output and a second comparator input. The second delay filter has an input coupled to an inverter output. The second comparator has a third comparator input coupled to a second delay filter output, and a fourth comparator input coupled to the second comparator input. The OR gate has an input coupled to a first comparator output and another input coupled to a second comparator output. The latch has a clock input coupled to an OR gate output and a latch input coupled to the inverter input. A latch output provides a deglitched signal.

Abstract: A transceiver that may be implemented in low-voltage differential signaling (LVDS) transmission system or a multipoint LVDS transmission system, and corresponding systems are disclosed herein. The transceiver can filter a common-mode component of a differential input signal input into the transceiver while maintaining a high impedance for a differential-mode component of the differential input signal. The transceiver utilizes teeter-totter circuitry to maintain the high impedance for the differential-mode component of the differential input signal.

Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

Abstract: A method of operating a driver circuit includes receiving a data signal at a first input of an amplification circuit; amplifying, using the amplification circuit, the data signal to produce an output signal through an output pin; attenuating, using a feedback network, the output signal to produce a feedback signal; coupling the feedback signal to a second input of the amplification circuit; detecting, using a control circuit, a fault condition; and decoupling, responsive to detecting the fault condition, the feedback signal from the second input of the amplification circuit. In some embodiments, the driver circuit transmits a fault condition signal to an electronic control unit of an automobile.

Abstract: Systems, apparatuses, and methods related to bit string operations in memory are described. The bit string operations may be performed within a memory array without transferring the bit strings or intermediate results of the operations to circuitry external to the memory array. For instance, sensing circuitry that can include a sense amplifier and a compute component can be coupled to a memory array. A controller can be coupled to the sensing circuitry and can be configured to cause one or more bit strings that are formatted according to a universal number format or a posit format to be transferred from the memory array to the sensing circuitry. The sensing circuitry can perform an arithmetic operation, a logical operation, or both using the one or more bit strings.

Abstract: A method, apparatus, system, and computer program product for quantum processing. A target quantum programming for a process for a quantum computer is identified. A universal gate set is selected based on a computer type. Any operation possible for a particular quantum computer can be performed using the universal gate set. Instructions for the process in a source quantum programming language are sent to a source quantum language translator which outputs a digital model representation of quantum computer components that are arranged to perform the process using the instructions. The digital model representation of the quantum computer components and the universal gate set are sent to a target quantum language translator, which outputs the instructions for operations for the process in a target quantum programming language using the digital model representation of the quantum computer components and the universal gate set for the computer type for the quantum computer.

Abstract: An ON/OFF detection device is configured to detect ON/OFF of an input unit using a load sensor, and includes a threshold setting unit, a comparison unit, and an ON/OFF determination unit. The threshold setting unit is configured to set a threshold value with respect to a previous detection value of the load sensor. The comparison unit is configured to compare the threshold value and a current detection value. The ON/OFF determination unit is configured to determine ON/OFF of the input unit based on a comparison result. When a previous determination result of the ON/OFF determination unit is ON, the threshold setting unit is configured to set the threshold value to be lower than the previous detection value. When the previous determination result of the ON/OFF determination unit is OFF, the threshold setting unit is configured to set the threshold value to be higher than the previous detection value.

Abstract: In circuitry for measuring a voltage at a node, a capacitive divider is coupled to the node, wherein the capacitive divider provides a first output. A resistive divider is coupled to the node, wherein the resistive divider provides a second output.

Abstract: A first terminal receives a first DC voltage. A switch selectively couples the first terminal to a second terminal providing an output. A control circuit selectively actuates the switch in response to a comparison of the first DC voltage to a second DC voltage. A low-dropout (LDO) linear voltage regulator, connected between the first and third terminals, operates to provide the second DC voltage from the first DC voltage.

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.